Matsushita Electric Industrial Co., Ltd.

Kazunari Yamaguchi

Kazuhiro Yamada

Atsuhisa Kageyama

Takahisa Hatano

Yoshikuni Shindo

Kazushige Kida

Hideki Abe

Noriyuki Iwakura

Synchronizing signal generator

The invention presents a dot clock reproducing apparatus for automatically reproducing the dot clock easily, by setting the dot clock frequency of a video signal source, and correcting the phase difference of the dot clock occurring in the transmission route or the like, and also presents a dot clock reproducing method comprising, in dot clock reproduction, a step of sampling at a frequency different from the dot clock of video signal, a step of detecting the aliasing frequency component occurring at this time, and a step of reproducing the dot clock so as not to cause this aliasing frequency component, and as an apparatus employing such method, the invention further provides a dot clock reproducing apparatus comprising A/D converting means for receiving an adjusting signal delivered from a video signal source, and sampling this adjusting signal to convert into a digital signal, PLL means for dividing a specified synchronizing signal and generating a sampling clock for the A/D converting means, frequency analyzing means for analyzing the frequency of the adjusting signal from the output of the A/D converting means, and dividing ratio setting means for controlling the dividing ratio of the PLL means from the output of the frequency analyzing means, wherein the dot clock is reproduced so that the output of the PLL means may be used as the dot clock signal, thereby realizing a dot clock reproducing apparatus for reproducing automatically the dot clock easily, by setting the dot clock frequency of the video signal source, and correcting the phase difference of the dot clock occurring in the transmission route or the like.

Dot clock reproducing method and dot clock reproducing apparatus using

A noise reducing apparatus includes a delay device for delaying a first video signal by one horizontal period. Also included is a first subtracter for subtracting the output of the delay device from an input video signal and a limiter for clipping the output of the first subtracter at a designated level. A variable coefficient-multiplier is also provided for multiplying the output of the limiter by a variable coefficient k where 0&lt;k&lt;1. A second subtracter subtracts the output of the variable coefficient multiplier from the input video signal and an adder adds the output of the first subtracter and the output of the limiter. A coefficient multiplier is also provided for multiplying the output of the adder by a fixed value 0.5. A third subtracter subtracts the output of the coefficient multiplier from the input video signal and a correlation detector provides a signal to control the coefficient value of the variable coefficient multiplier in response to the output of the first subtracter.

Noise reducing apparatus

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Sapporo, Japan

Kazunari Yamaguchi