Matsushita Electric Industrial Co., Ltd.

Panasonic Intellectual Property Management Co., Ltd.

Nuvoton Technology Corporation Japan

Kazunari Takahashi

Masashi Agata

Naoki Kuroda

Tsutomu Fujita

Susumu Fukushima

Masanori Shirahama

Takeshi Nakano

Toshio Yamada

Junji Ito

Ryuji Nishihara

Hiroyuki Sadakata

Keita Sakai

Takashi Ishimura

Nobuhiko Mutoh

Tomoko Maeda

Kouji Shimomura

Kaoru Kudou

Masayuki Fujioka

Provided is a sensing system that performs set control with high sensing accuracy. The sensing system that outputs an object signal includes a solid-state imaging device that senses a first physical target from an object and a second physical target different from the first physical target, and an arithmetic operation unit that calculates an object signal using a first signal from the first physical target and a second signal from the second physical target. The arithmetic operation unit calculates an object signal using a reference signal from a device mounted with the sensing system.

Sensing system and driving support system

The present disclosure makes it possible to perform a failure diagnosis of an electric two-wheeled vehicle easily, conveniently, and immediately. The electric two-wheeled vehicle includes an electric equipment unit having an IC tag and a host unit. The host unit is capable of communicating with the IC tag, and obtains failure information of the electric equipment unit while electric power is supplied from the battery to the electric equipment unit. The information communication terminal obtains the failure information by communicating with the electric two-wheeled vehicle in a non-contact manner, and transmits the failure information to the server via the network. The server performs a failure diagnosis on the electric two-wheeled vehicle based on the failure information.

Information processing system for electric two-wheeled vehicle, electric two-wheeled vehicle, electric equipment unit, and key for electric two-wheeled vehicle

The semiconductor memory device includes: a memory cell including a capacitor having a charge storage node and a first MIS transistor and a second MIS transistor each having a source connected to the charge storage node; a first word line and a first bit line respectively connected to the gate and the drain of the first MIS transistor; a second word line and a second bit line respectively connected to the gate and the drain of the second MIS transistor; and a timer circuit for generating a periodic signal having a predetermined period. The first word line or the second word line is activated in response to the periodic signal.

Semiconductor memory device

A semiconductor memory device has a plurality of memory cells each having a first transistor, a second transistor having a source or drain connected to one portion of the source or drain of the first transistor, and a third transistor having a source or drain connected to the other portion of the source or drain of the first transistor. The first transistor accumulates, in the channel thereof, charges transferred from the second and third transistors.

A semiconductor integrated circuit is disclosed which includes a clock synchronous memory, an internal clock generating circuit, a clock selecting circuit, a data output converting circuit, and a data output selecting circuit. The clock synchronous memory is disposed to receive a control signal, an address signal, and a data input and provide an internal data output. The internal clock generating circuit is disposed to generate an internal clock signal having a frequency higher than that of an external clock signal. The clock selecting circuit is disposed to select between the external clock signal and the internal clock signal and send the selected clock signal to the clock synchronous memory. The data output converting circuit is disposed to convert the internal data output into an external data output in synchronization with a clock signal having a frequency lower than that of the internal clock signal. The data output selecting circuit is disposed to select between the internal data output and the external data output and provide the selected data output.

Semiconductor integrated circuit

In a semiconductor memory device with multiple memory cells, each including a charge storage device and two transfer devices for transferring its charge, these memory cells are accessible with no select signal provided externally. The memory device includes a clock generator for generating first and second mutually complementary clock signals. In response to the first and second clock signals, one of first word lines and one of second word lines are activated alternately. Specifically, the first clock signal makes a memory cell accessible through a first bit line by activating the first word line and first transistor, while the second clock signal makes the memory cell accessible through a second bit line by activating the second word line and second transistor.

Low latency dynamic random access memory

The semiconductor storage device of this invention includes memory cells each having two transistors and one storage capacitor. Each memory cell is connected with a first word line and a first bit line for a first port and a second word line and a second bit line for a second port. The first and second bit lines are alternately disposed in an open bit line configuration. In the operation of the semiconductor storage device, in a period when a first precharge signal for precharging each first bit line or a first sense amplifier activating signal for activating a first sense amplifier is kept in an active state, a second precharge signal for precharging each second bit line and a second sense amplifier activating signal for activating a second sense amplifier are both placed in an inactive state.

Semiconductor storage device

A cache memory including a first memory array and a main memory including a second memory array are integrated together on the same semiconductor substrate. Each memory cell in the first memory array is of a 2Tr1C type including: first and second transistors, the sources of which are connected together; and a data storage capacitor, one of the two electrodes of which is connected to the common source of the first and second transistors. Each memory cell in the second memory array is of a 1Tr1C type including: a third transistor; and a data storage capacitor, one of the two electrodes of which is connected to the source of the third transistor.

Over an active region with two bent portions on a semiconductor substrate, first and second word lines extend to cross these bent portions and to be vertically spaced apart from each other. Around at the center of the active region, a capacitor for storing data thereon and a capacitor contact are formed. A first bit line contact, which is connected to the active region, is formed on the opposite side to the capacitor contact across the first word line over the active region. A second bit line contact, which is also connected to the active region, is formed on the opposite side to the capacitor contact across the second word line over the active region. These first and second bit line contacts are provided substantially symmetrically about the center of the memory cell. In a pair of memory cells adjacent to each other along bit lines, one vertical end of the active region in one of the memory cells is continuous with an associated vertical end of the active region in the other memory cell. And each of the first and second bit line contacts is shared between an adjacent pair of memory cells.

Growing community of inventors

Shiga, Japan

Kazunari Takahashi