Fujitsu Corporation

Kazunari Shirai

Izumi Tanaka

Taiji Ema

Hajime Kamioka

Shinpei Tanaka

Keiji Nishimoto

Shigeyoshi Koike

Semiconductor device

A semiconductor device having contact windows between an aluminum or aluminum-alloy wiring layer and a diffused region in a semiconductor substrate, in which the contacts are formed by using a barrier film on a refractory metal silicide between the wiring layer and the diffused region. The barrier film comprising the refactory metal and silicon is beam annealed for a short period of time such as, 10 seconds or less, so that adverse effects of the barrier film can be prevented while an excellent electrical or ohmic contact between the wiring layer and the diffused layer can be obtained.

Beam annealed silicide film on semiconductor substrate

The present invention is an improvement of a semiconductor memory device, preferably a PROM or a mask ROM, wherein: MOS transistors are formed in a semiconductor substrate, are arranged in rows, and are isolated from each other by a plurality of field insulation films arranged in an island pattern; the MOS transistors aligned in one of the rows have one common gate which extends over one row of field insulation films; the MOS transistors aligned in one of the rows have a common first region for forming a drain or a source parallel to the common gates; and a second region for forming another drain or source is surrounded by a pair of common gates and a pair of field insulation films so that a plurality of second regions are isolated from each other. According to the present invention, the field insulation films and the common gates are delineated to coincide with one another at the ends thereof facing the common first region using a mask film extending between a pair of common gates and covering the region between the pair of common gates and the part of the common gates not covered by the mask film.

Semiconductor memory device and process for producing the same

An improved semiconductor memory device is provided, which has: (i) a first gate electrode in an electrically floating state, at least a part of which confronts a channel region of a semiconductor device and which is separated by an insulating layer from the channel region; (ii) a second gate electrode (i.e., a control electrode), at least a part of which confronts the first gate electrode and is separated by an insulating layer from the first gate electrode; and (iii) a third gate electrode (i.e., an erasing electrode), at least a part of which confronts the first gate electrode and is separated by an insulating layer from the first gate electrode. The insulating layer, separating at least a part of the erasing electrode from the first gate electrode, has a thickness (usually 50 to 300 A) sufficient to allow the passage of charges from the first gate electrode to the erasing electrode through a tunneling effect, thereby discharging the first gate electrode.

Semiconductor memory drive

A plural layered wiring which comprises a plurality of polycrystal semiconductor layers can be improved in its magnitude of circuit integration, when one or more upper polycrystal semiconductor layers which is or are doped to a moderate impurity concentration is or are utilized as resistor elements, the lowest polycrystal semiconductor layer which is highly doped is utilized for electrodes and/or wirings for active elements, and both polycrystal layers are connected with each other by regions which are highly doped by upward diffusion of impurities contained in highly doped regions of a substrate, because this configuration entirely avoids the restriction that is imposed for the location of resistor elements arranged in the upper layers. This arrangement is realized by a specific sequential combination of steps which includes a step of upward diffusion of impurities from the highly doped regions of the substrate. An additional advantage of this method is the exclusion of a so-called non-butting process.

Semiconductor device and method for production thereof

A polycrystalline silicon is used for a resistor element of a semiconductor device instead of a conventional, diffused resistor or a channel resistor, in which the channel resistance of an MOS transistor is utilized as the resistor. The length of a polycrystalline silicon layer for the resistor element is predetermined by the other polycrystalline silicon layer, formed above the resistor element. The structure of the semiconductor device according to the present invention is suited for a high density integrated circuit.

Semiconductor device and process for producing the same

In a method of smoothing the edges of a window through a PSG film of a semiconductor device, a masking film is provided under the PSG film, so as to prevent impurities of the PSG film from penetrating into semiconductor substrate during the heating of the PSG film for the smoothing of the edges. A masking film, for example, an Si.sub.3 N.sub.4 film, does not, however, inhibit the penetration of hydrogen gas, which can improve the properties of an MIS semiconductor device.

Growing community of inventors

Yokohama, Japan

Kazunari Shirai