Spansion LLC.

Fujitsu Corporation

Kazunari Kido

Minoru Yamashita

Kazuhiro Kurihara

Yasushi Kasa

Hiroaki Wada

Atsushi Hatakeyama

Yuichi Einaga

The semiconductor device includes a memory cell array that includes memory cells for storing data and is managed on a sector basis, a memory that stores the information determining the activation status, a latch circuit that latches the activation information according to the information stored in the memory, and a circuit that latches the activation information according to the information stored in the memory in the latch circuit. The activation information according to the memory state of the memory is latched at the time of inputting a given command after activation, and it is thus possible to read the information stored in the memory and set the information in the latch circuit certainly.

Semiconductor device and control method of the same

A semiconductor device includes a first memory cell array that includes memory cells for storing data and is managed on a sector basis, a second memory cell array including memory cells storing sector protection information on the sector basis, and a control circuit checking the sector protection information stored in the second memory cell array whenever the sector to be programmed or erased is selected. Thus, the sector protection information in all the sectors does not have to be latched at the time of power on. The latch circuit equal in number to the sector does not have to be provided. It is thus possible to reduce the number of the circuits drastically and the chip area can be reduced.

Semiconductor memory device and control method having data protection feature

The semiconductor device of the present invention includes at least one dummy cell of a programmed state proximately located to an edge of a reference cell array. Thus, the leak current does not flow when a data of the cell on the edge of the reference cell array is read out. The memory cell located around the center of the reference cell array has neighboring cells of the programmed state, and the leak current can be prevented when the data is read out from all the reference cells. Thus, the reference current can be supplied stably.

Semiconductor device and programming method

A semiconductor memory that prevents a decrease in margin at read time. A bit line in a floating state between a drain in a memory cell to be read and a charged bit line is charged for a certain period of time.

Non-volatile semiconductor memory that is based on a virtual ground method

The input/output nodes of memory cells connected in series are connected to bit lines. Two of the bit lines positioned on the outsides of four successive memory cells constitute each of a plurality of bit line pairs. The bit line pairs are connected to four data lines, respectively, via switches connected to the respective bit lines. A switching control circuit turns on adjacent five of the switches. A switching circuit connects the data lines connected to the input/output nodes by the turning-on of the switches to a supply node of a first voltage, a supply node of a second voltage, and first and second sense amplifiers, respectively. Thereby, data is read from two of the memory cells simultaneously. Thus, it is possible to read data from the two memory cells simultaneously by using the simple switching control circuit without increasing the chip size.

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Kanagawa, Japan

Kazunari Kido