Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Renesas Electronics Corporation

Fujitsu Corporation

Miharu Communications Co., Ltd.

Kazunari Inoue

Hideaki Abe

Hideto Matsuoka

Hiromi Adachi

Kazutami Arimoto

Akira Yamazaki

Katsumi Dosaka

Koji Nii

Takeshi Fujino

Junko Matsumoto

Toshiyuki Ogawa

Shigefumi Masuda

Yoshio Fudeyasu

Yuji Yano

Kaori Mori

Yuko Ozeki

Hisashi Iwamoto

Minoru Ishida

Hiroo Tamura

Koji Uruma

Hiroshi Oshita

Hiroshi Ohshita

Takayuki Tyou

A semiconductor device includes a plurality of memory arrays and a plurality of memory array control circuits. Each of the plurality of memory array control circuits includes a read/write control circuit for controlling a read/write operation for the memory array, and a selection circuit for selecting and activating the memory array based on a clock signal and an output signal from the read/write control circuit.

Semiconductor device including memory capable of reducing power consumption

Array area and power consumption are reduced in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and mask cells for storing mask bits. The number of mask cells is smaller than that of the data storage cells. Search data is transmitted to the comparator via a search data bus. One of the entries is selected according to a predetermined rule. The comparator decodes the mask bits, generates a mask instruction signal, and performs match comparison and size comparison between the search data and data to be retrieved which is stored in the selected entry.

Content addressable memory

The present invention is directed to reduce array area and power consumption in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and mask cells for storing mask bits. The number of mask cells is smaller than that of the data storage cells. Search data is transmitted to the comparator via a search data bus. One of the entries is selected according to a predetermined rule. The comparator decodes the mask bits, generates a mask instruction signal, and performs match comparison and size comparison between the search data and data to be retrieved which is stored in the selected entry.

A plurality of content-addressable-memory sub-arrays simultaneously performs a parallel comparison between data sequences arranged in a row direction of memory cells and a search data sequence input from outside, and outputs a result of the comparison for each data sequence. A first input pin receives an input of the search data sequence. A second input pin receives an input of a search data sequence arbitrarily designating a content-addressable-memory sub-array. Each of the content-addressable-memory sub-arrays includes an activation control unit that controls activation of the content-addressable-memory sub-arrays based on the search data sequence.

Low-power content-addressable-memory device

Low power content-addressable-memory device

A TCAM (ternary content addressable memory) cell array is provided with a search input node into which one bit of search data is inputted, a plurality of data input nodes into which a bit corresponding to one bit of search data is inputted, and a plurality of memory cells arranged in rows and columns. Each of the plurality of memory cells further includes a first cell storing one bit of said storage data, and a logical operation cell determining whether or not said search data and storage data match. A gate of a transistor forming each of a plurality of memory cells extends along the direction of said rows. Each of a plurality of wells in the region where the memory array is formed is formed so as to continue to a corresponding well of an adjacent memory cell in the direction of said columns.

Highly integrated ternary semiconductor memory device

A search payload data shift part has n latch parts LTto LTn (n&#x2267;2), each of which can store 1-byte latch data, and obtains search payload data having an n-byte length, while shifting payload data inputted from an input terminal, in synchronization with a clock provided from the exterior. Data related to the search payload data is given to a CAM array, as search object data. When the search object data matches entry data of the CAM array, a hit signal 'hit' indicating a match is outputted from the CAM array.

Integrated circuit with associated memory function

The present invention concerns an ingress noise control system and an ingress noise blocking device which are used in a cable system to suppress ingress noise. In the cable system providing two-way communication using different frequency bands for transmission of upstream and downstream signals, the ingress noise control system includes, within a distribution unit, a two-way amplification unit, etc. provided in an upstream signal transmission path, a synchronous detection controllerfor synchronously detecting the upstream signal transmitted from terminal equipment and separated by a low-pass filterin a second separation filter, a gate switch circuitwhich is turned on by the synchronous detection controllerto pass the upstream signal only when the upstream signal is synchronously detected, and an indicatorfor indicating the on/off state of the gate switch circuit

Ingress noise control system and ingress noise blocking device

A semiconductor memory can reduce its power consumption by decreasing the activation frequency of search lines during search operation. It includes a CAM cell block for storing memory data expressing each combination of digital values stored in four memory cells in terms of a 2-bit digital value; search lines on which a digital value to be matched with a digital value stored in the memory cells is placed; a search data setting section for placing individual 1-bit digital values on the search lines connected to the memory cells to set the search data expressing a 4-bit combination of digital values in terms of the 2-bit digital value; transistors for deciding match/mismatch between the memory data and search data; and the match line for outputting the decision result.

Semiconductor memory

A content addressable memory (CAM) cell array includes a first-stage memory cell array and a second-stage memory cell array. Only when data on search output lines (match lines) connected to the first-stage memory cell array are coincident, the second-stage memory cell array performs search operation. Therefore, power consumption of the CAM cell array can be reduced.

CAM cell array, TCAM cell, TCAM cell array, address search memory, and network address search apparatus

A central row-related control circuit transmits an internal row address signal to each memory sub block in banks of memory mats asynchronously with an external clock signal, and latches a block selection signal for specifying a memory sub block synchronously with an internal clock signal for one clock cycle period for transmission to each memory sub block. A spare determination circuit performs spare determination asynchronously with the clock signal. A semiconductor memory device easily adaptable to bank expansion without increase of the chip area and capable of implementing a high speed access can be provided.

Semiconductor memory device having row-related circuit operating at high speed

A semiconductor integrated circuit device latches externally applied signals received through input/output pads at registers. Signals output from registers are applied to an internal circuit through a switching circuit. Switching circuit is controlled by a signal MIRROR/EN to invert mirror-symmetrically the relation of the signals applied to the internal circuit and the input/output pads.

Semiconductor device capable of mirror-symmetrically inverting

A DRAM includes a data transfer pipeline register group between a dynamic memory cell array and a static memory cell array, a first unidirectional read bus and a first unidirectional write bus connected between a data transfer bus group and the data transfer pipeline register group, and a second unidirectional write bus and a second unidirectional read bus connected between the data transfer pipeline register group and the static memory cell array. The operating frequency of the second unidirectional write bus and the second unidirectional read bus is N times the operating frequency of the first unidirectional read bus and the first unidirectional write bus. The number of lines of the second unidirectional write bus and the second unidirectional read bus is 1/N time the number of lines of the first unidirectional read bus and the first unidirectional write bus. The dynamic memory cell array is further divided into a hierarchical manner of main banks and subbanks.

Semiconductor memory device accessible at high speed

A frame buffer memory includes, on a semiconductor substrate: a DRAM array in which image information including frame information and window information are stored; two serial access memories for serially outputting the image information read from DRAM array by interleave method; a look-up table for outputting a selection signal in accordance with window information input; and a multiplexer for selectively outputting frame information input in accordance with said selection signal.

Growing community of inventors

Hyogo, Japan

Kazunari Inoue