Nippon Electric Co., Ltd.

Nec Corporation

Nippon Telegraph and Telephone Corporation

Nec Corporation and Nippon Telegraph and Telephone Corporation

Kazumoto Iinuma

Yukihiko Iijima

Hideo Hashimoto

Tatsuo Ishiguro

Toshio Koga

Naoki Mukawa

Akihiro Furukawa

Hideo Kuroda

Touru Usubuchi

Sakae Okubo

Takanori Sashida

The invention provides an information network system and a broadcasting receiving user terminal by which bidirectional communication can be established between a user terminal and a data base center and between the data base center and a broadcasting station so that a user can enjoy a service provided from the data base center and enjoy bidirectional communication in regard to broadcasting. The information network system includes a broadcasting receiver, a user terminal, and a data base center connected to the user terminal by a network. The broadcasting center includes a guide information addition section which adds data base accessing guide information to a broadcasting signal for a program to be transmitted. The user terminal includes a guide information extraction section which extracts the guide information from the broadcasting signal, and a network communication section which accesses a data base of the data base center via the network based on the extracted guide information and user information peculiar to a user of the user terminal and receives a response from the data base center. The data base center includes another network communication section which confirms the guide information and the user information received from the user terminal via the network and then establishes bidirectional communication with the user terminal.

Information network system making use of television or radio broadcasting and broadcast receiving user terminal

In a predictive encoder for use particularly in a conference television system, a signal processing unit is used in producing a prediction signal and comprises three prediction circuits (22, 23, 31) and a selection circuit (24) coupled to the prediction circuits. The prediction circuits are for producing an inframe, an interframe, and a background prediction signals, respectively. Those signals are produced by processing an original signal at instants which precede a current instant and are different from one another. The selection circuit is for selecting one of the inframe, the interframe, and the background prediction signals. Therefore, it is possible to produce the prediction signal suitably predictive of the original signal. The signal processing circuit serves equally well in a predictive decoder.

Signal processing unit for producing a selected one of signals

A predictive coding/decoding system for block-formed picture signals includes predictive coding and decoding units in transmitter and receiver sides, respectively: each of the predictive coding and decoding units is provided with a control pulse generator responsive to a horizontal synchronization pulse in the picture signal to produce a sampling signal and a select signal, and a pair of selectors together responsive to the select signal to select a sum of a prediction signal and a prediction error signal or a fixed value as an input of a prediction circuit, the pair of selectors selecting the fixed value for a partial picture block including a fraction of pixels due to the block formation.

Predictine coding/decoding system for block-formed picture signals

In a code conversion system comprising an encoder and a decoder in combination, the encoder comprises an input terminal for receiving a multi-level time series signal having at least three signal levels subject to a variation of occurrence frequency of levels, a circuit for detecting the highest occurrence frequency signal ('HOFS') level of said multi-level time series signal and generating a first code representative of the run-lengths of said HOFS level, a circuit for generating a second code representative of the individual levels of said multi-level time series signal, and a circuit for combining said codes from said first and second code generation circuits on the time series, and wherein the decoder comprises a circuit for separating the first and second codes and decoding the separated first and second codes into the original multi-level time series signal.

Code conversion system

A prediction error signal and a prediction state signal are generated for each of a plurality of picture elements (or bit planes or gray codes) to be encoded. The picture error signal is based on a plurality of previously encoded picture element data (or bit plane or gray code). The prediction state signal indicates the probability of the prediction error signal being accurate in one of two probability states. The prediction error signals are classified into two groups according to the probability state indicated by the corresponding prediction state signal. The prediction error signals are then reordered according to a predetermined algorithm. Thereafter, the reordered prediction error signals are run length coded based on the occurrences of incorrectly predicted error signals in the reordered list.

Method of processing picture signal to increase average run length and

In a run length decoding apparatus of the type comprising a decoding circuit decoding a series of run length encoded data to sequentially output binary data indicative of respective run lengths, and decoding means for decoding a white or black signal having a number of bits represented by an output value of the decoding circuit so as to sequentially accumulate decoded signals in a picture memory device, there are provided a lower order counter to be set with a surplus less than n (an integer larger than 2) of the output value of the decoding circuit, an upper order counter to be set with an upper order value, count of the upper order counter being decremented according to a clock pulse, a selector which, in response to a carry signal outputted by the upper order counter, selects and outputs either one of a fixed value n and an output signal of the lower order counter at each clock pulse, a flip-flop circuit whose state is reversed at each one run length, and an array conversion circuit inputted with decoded data outputted from the flip-flop circuit and a number of effective data outputted from the selector to sequentially array effective decoded data for outputting them as parallel data each having more than n bits.

Run length decoding apparatus

In an encoder responsive to a video signal variable between high and low levels, a logic converter logically converts a succession of result signals, derived from the video signal by the use of a predetermined number of halftone threshold levels, into a sequence of converted signals having that run length of logic '0' or '1' level which is longer than that in the result signal succession. The converter may comprise a combination of adders and memory elements to process the consecutive result signals. The converted signal sequence is encoded by an encoding circuit into a data-compression digitized signal. In a decoder for decoding the digitized signal into a reproduction of the result signal succession, a logic inverter comprises a combination of adders and memory elements, similar to that of the converter. The inverter processes, into the reproduction, signals derived from data-expansion decoding of the digitized signal. Preferably, a dither matrix is used to provide the threshold levels.

System for transmitting a video signal with short runs avoided in a

Code converting circuits for facsimile and other information communications systems in which run length codes are converted to codes having variable lengths and the variable length codes are converted into a word code train, wherein each word comprises N bits, and the converted word code train is stored or transmitted. The code converting circuit consists of a code converter for converting parallel input codes (run length codes of fixed lengths) into variable length codes, a multiplexer and shift register for converting the variable length codes (and dummy codes where needed) into word length codes of fixed length, a multiplexer for outputting the word length codes to a memory interjecting a synchronizing code at predetermined intervals, and control signal generating circuitry for controlling the various circuit components. A decoding circuit is also disclosed for reconstructing the original run length codes from the word length codes. In addition, a second embodiment is disclosed which uses a parallel signal processing technique and is particularly adapted for encoding and decoding television video signals.

Code converting circuits

A digital facsimile system suitable for the facsimile transmission of newspaper pages having screened picture portions and printed character portions is disclosed. The transmitter receives a digitized facsimile signal which is a train of pel codes formed by scanning a picture to be transmitted. In response to the digitized facsimile signal, a first reference generator produces first pel codes neighboring the present pel code, a second pel code spaced by the pitch of the screened picture from the present pel code, and third pel codes neighboring the second pel code. A ROM is addressed by the first, second and third pel codes to produce a first prediction code for the present pel code. The output of the ROM and the digitized facsimile signal are supplied to an Exclusive OR which provides a prediction error code according to the difference between the first prediction code and the present pel code. A train of prediction errors codes constitutes a prediction error signal which is encoded and transmitted. The receiver receives the encoded prediction error signal and decodes it to reproduce the prediction error signal. Another Exclusive OR produces the present pel code from each error code of the prediction error signal. A second reference code generator produces a second reference code corresponding to the first reference code on the basis of the output of the second Exclusive OR. A second ROM produces a second prediction code corresponding to the first prediction code on the basis of the second reference code and applies the second prediction code to the second Exclusive OR.

Digital facsimile transmission system for screened pictures

An interframe encoder for a composite color television signal comprises an inverter for inverting the polarity of the carrier chrominance signal. Responsive to a switching signal synchronized with the frame or line periods, the television signal and the polarity-inverted signal are alternatingly switched into a converted signal in which the polarity of the carrier chrominance signal is inverted in every other frame or line period. The converted signal is interframe encoded. An interframe decoder reproduces the converted signal and the switching signal and comprises an inverter for inverting the polarity of the reproduced carrier chrominance signal. Responsive to the reproduced switching signal, the reproduced and polarity-inverted carrier chrominance signal and the converted signal are switched into a reproduction of the color television signal.

Interframe CODEC for composite color TV signals comprising means for

A system carries out predictive encoding or decoding by selecting a prediction signal for a longer period among two or more prediction signals at the beginning of an autocorrelated signal to be encoded or of a prediction error signal to be decoded. At least one of the prediction signals may be a composite prediction signal. A sampling interval after each instant at which the prediction error signal exceeds in absolute value a threshold level, the encoding or decoding is carried out with the prediction signals switched from one to another. A control circuit for two prediction signals comprises a two-input Exclusive OR gate supplied with a result of comparison of the prediction error signal with the threshold level and a sample delay supplied with the Exclusive OR output. The delayed signal is supplied back to the Exclusive OR gate and forward to a switch for switching the prediction signals.

Predictive encoder or decoder with selection of one of two or more

Responsive to signal samples of a color television signal including a carrier chrominance signal, a predictive encoder produces quantized prediction error signals in compliance with a first transfer characteristic (1 - P.sub.1)(1 - P.sub.2), wherein minima which are substantially equal to zero are taken by the absolute value of 1 - P.sub.1 in the neighborhood of frame frequency and by the absolute value of 1 - P.sub.2 in the neighborhoods of zero frequency and subcarrier frequency. Responsive to the quantized prediction error signals, a predictive decoder produces reproduced samples in compliance with a second transfer characteristic of the inverse of the first transfer characteristic.

Growing community of inventors

Tokyo, Japan

Kazumoto Iinuma