Hitachi, Ltd.

Kazumichi Yamamoto

Kentaro Shimada

Makoto Hanawa

Kenji Kaneko

Noboru Masuda

Minoru Yamada

Keiichirou Nakanishi

Tatsuya Saitoh

Akira Yamagiwa

Muneaki Yamaguchi

Yukio Fujii

Kazuo Koide

Kazunori Nakajima

Bunichi Fujita

Toshihiro Okabe

Seiichi Kawashima

Moritoshi Yasunaga

Masao Ishiguro

Mikio Yamagishi

Katsunari Shibata

Norihiro Suzuki

Akira Yonekawa

Yukio Umetani

Naofumi Tomita

Within a television broadcast recording/reproducing apparatus, for preventing a commercial message (CM) from being cut when viewing an abridgement (digest), and for presenting the CM to a viewer without losing an advantage of viewing the abridgement, a ranking value of a CM portion is changed, with using a means for evaluating video and audio by one (1) frame thereof, thereby to give a ranking value thereto, and a means for detecting a CM portion.

Video recording/reproducing apparatus having commercial view control function

The present invention relates to a cache mechanism of a browser apparatus as a World Wide Web (WWW) client and aims at the improvement of utilization efficiency and the shortening of an information acquisition delay time. A cache is constituted in an HDD or DVD-RAM under the control of a Web cache program. A copy of acquired information is stored in the cache. A directory of the cache is managed by a Web cache management table, and the control is made so that the writing of the cache contents and necessary entries of the management table is completed before the DVD-RAM is removed from the browser apparatus. A browsing work can be continued smoothly by loading the DVD-RAM to another browser apparatus. Also, if an information provider provides information in a form stored in a disk in the form of a Web cache, the browsing of the information becomes possible with the same URL as that in WWW access.

Web cache memory device and browser apparatus utilizing the same

In a cache memory of a super-scalar or VLIW processor to concurrently process a plurality of memory accesses, to provide a memory capable of multi-port access operation, there is provided a unit which subdivides the cache memory into a plurality of memory banks for concurrent operations thereof and which allocates memory ports independently to the respective memory banks. In a first cycle, the first and second memory ports are allocated to the first and second memory banks, respectively. If a hit occurs, the plural accesses are completed in one cycle. If a miss results, the first and second memory ports are allocated respectively to the second and first memory banks in a second cycle.

Multi-port memory and a data processor accessing the same

To improve the efficiency of instruction branch operations, particularly in a pipeline processor, a branch reservation instruction is generated during program compile. The system includes a processor having a branch address stack 10 for storing pairs of branch point addresses and branch target addresses, a program counter (PC) 12 which holds a current instruction fetch address, a comparator 11 which compares the branch point address of the most recently entered pair stored in the stack 10 and the value of the PC 12, and a selector 14 which, when the result of comparison shows the coincidence, switches the instruction fetch address from the value of the PC 12 to the branch target address of the most recently entered pair stored in the stack 10. The branch operation is performed by reserving a pair of a branch target address and a branch point address in the stack 10 by a branch reservation instruction in advance of the branch point in the instruction sequence, and switching the next instruction fetch address to the branch target address promptly when the instruction fetch reaches the branch point.

Instruction branching method and a processor

System with reservation instruction execution to store branch target

A variable delay circuit including delay devices each having a plurality of delay units connected successively, only some of the delay units of the delay devices being connected to a signal transmission line, wherein a delay time is controlled by activating or inactivating the plurality of delay units according to control signals applied to control input terminals provided respectively for said plurality of delay units. A clock signal supply device for supplying a second clock signal to a logic circuit block, said clock signal supply device having a clock signal generator for generating a first clock signal and a reference signal and a phase adjusting means for adjusting the phase of the first clock signal phased on a phase difference between the first clock signal and the reference signal and outputting the phase-adjusted signal as a second clock signal, wherein the phase adjusting unit comprises a first variable delay circuit capable of delay operation in initial adjustment of the first clock signal, a second variable delay circuit, disposed in series with the first variable delay circuit, for performing the delay operation after the initial adjustment, and control circuits for controlling delay times of the first and second variable delay circuits.

Variable delay circuit and clock signal supply unit using the same

A semiconductor integrated circuit device includes a plurality of integrated circuit chips and a large-sized integrated circuit element on which the plurality of integrated circuit chips are mounted. The large-sized integrated circuit element includes a logic circuit for electrically interconnecting the integrated circuit chips mounted on it. The logic circuit provided within the large-sized integrated circuit element includes a control circuit for controlling a connection relation between the integrated circuit chips mounted on the large-sized integrated circuit element. Further, the logic circuit includes buffer or latch circuits for relaying signals transmitted between the integrated circuit chips.

Semiconductor integrated circuit device and computer system using the

This invention discloses an integrated circuit device including an integrated circuit chip having logic circuits formed therein and a wiring substrate for mounting thereon the integrated circuit chip. The wiring substrate has signal wirings for connecting mutually input terminals and output terminals of the integrated circuit chip. The integrated circuit device includes signal wirings for effecting connections of the input terminals and output terminals of the same integrated circuit chip inside the wiring substrate. The logic circuits inside the same integrated circuit chip are mutually connected by signal wirings formed inside the integrated circuit chip when a wiring length is small, and are mutually connected by signal wirings formed inside the wiring substrate when the wiring length is great.

Integrated circuit device having an ic chip mounted on the wiring

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Ebina, Japan

Kazumichi Yamamoto