Kabushiki Kaisha Toshiba

Kazumi Inoh

Takashi Yamada

Satoshi Matsuda

Shigeru Kawanaka

Yasuhiro Katsumata

Tsutomu Sato

Ichiro Mizushima

Tsuneaki Fuse

Hiroomi Nakajima

Tomoaki Shino

Yoshihiro Minami

Makoto Yoshimi

Hideaki Nii

Hidemi Ishiuchi

Sadayuki Yoshitomi

Chihiro Yoshino

Takeshi Hamamoto

Tatsuya Ohguro

Hajime Nagano

Hiroaki Yamada

Kenji Kojima

Atsushi Azuma

Mamoru Terauchi

A semiconductor memory device comprises a substrate; a semiconductor layer of a first conductive type isolated from the substrate by an insulator layer; a memory transistor having a gate electrode, a drain and a source regions of a second conductive type formed in the semiconductor layer, and a channel body of the first conductive type formed in the semiconductor layer between the regions, the memory transistor operative to store data as a state of majority carriers accumulated in the channel body; an impurity-diffused region of the first conductive type formed at a location in contact with the upper surface of the drain region, the impurity-diffused region having a higher impurity concentration of the first conductive type than an impurity concentration of the second conductive type in the drain region; and a write transistor including a bipolar transistor having the impurity-diffused region as an emitter region, the drain region as a base region and the channel body as a collector region, the write transistor operative to write data in the memory transistor.

Semiconductor memory device for storing data as state of majority carriers accumulated in channel body and method of manufacturing the same

A silicide film is provided in diffusion regions formed in a semiconductor layer. The silicide film has a thickness substantially same as that of the semiconductor layer. The silicide film has the bottom located in the vicinity of an interface between the insulator film and the semiconductor layer.

Semiconductor memory device

A semiconductor device includes a semiconductor substrate, cavities, and an element isolating region. The cavities, which are each shaped like a flat plate, are made in the semiconductor substrate. The element isolating region is formed in the surface of the semiconductor substrate and located at the sides of the cavities.

Semiconductor device with a cavity therein and a method of manufacturing the same

A semiconductor device includes first and second gate electrode, first and second gate insulating film, semiconductor layer, source and drain regions, and source and drain electrodes. The first gate electrode is formed in the insulating film. The first gate insulating film is formed on the first gate electrode. The semiconductor layer is formed on the insulating film. The source and drain regions are formed in the semiconductor layer. The source and drain electrodes are respectively formed on the source and drain regions. The positions of side wall surfaces of the source and drain electrodes which face each other are substantially aligned with the positions of both side wall surfaces of the first gate electrode in a direction perpendicular to the surface of the insulating film. The second gate insulating film is formed on the semiconductor layer. The second gate electrode is formed on the second gate insulating film.

Semiconductor device having a plurality of gate electrodes and manufacturing method thereof

A convex polycrystalline silicon film is formed on a handle wafer. A semiconductor layer is formed on the polycrystalline silicon film. The semiconductor is thinner on its areas in which the convex polycrystalline silicon film is formed and is thicker on its areas in which the convex polycrystalline silicon film is not formed. An opening is formed in each of those areas of an insulating film which are located under respective thick-film semiconductor areas of the semiconductor layer. The polycrystalline silicon film is formed in the openings to connect electrically the thick-film semiconductor areas and the handle wafer together.

Semiconductor device comprising plurality of semiconductor areas having the same top surface and different film thicknesses and manufacturing method for the same

A semiconductor device comprises: a semiconductor substrate; an insulating layer provided on said semiconductor substrate; a first semiconductor layer provided on said insulating layer; a plurality of openings penetrating said first semiconductor layer and said insulating layer and reaching said semiconductor substrate; and second semiconductor layers filling said openings by selective growth and connected to said semiconductor substrate, wherein areal sizes of said plurality of openings are substantially equal to each other.

Semiconductor device

In a bipolar transistor improved to exhibit an excellent high-frequency property by decreasing the width of the intrinsic base with without increasing the base resistance, an emitter region, intrinsic base region and collector region are closely aligned on an insulating layer, and the intrinsic base region and the collector region make a protrusion projecting upward from the substrate surface. The protrusion has a width wider than the width of the intrinsic base region.

Lateral bipolar transistor formed on an insulating layer

In a lateral bipolar transistor, its emitter region, base region, link base region, and so forth, are made in self alignment with side walls of masks by using partly overlapping two mask patterns. Therefore, not relying on the mask alignment accuracy, these regions are made in a precisely controlled positional relation. Thus, the lateral bipolar transistor, thus obtained, is reduced in parasitic resistance of the base and parasitic junction capacitance between the emitter and the base, and alleviated in variance of characteristics caused by fluctuation of the length of a link base region, length of the emitter-base junction and relative positions of the emitter and the collector, and can be manufactured with a high reproducibility.

Method for manufacturing a lateral bipolar transistor

To obtain both the highest possible maximum operating frequency f.sub.max and early voltage V.sub.A, a semiconductor device provided with a bipolar transistor including a collector region, a base region formed on the collector region, an emitter region formed in contact with the base region, a base leading electrode connected to the base region, and an emitter electrode connected to the emitter region, is characterized in that a ratio Q.sub.B /N.sub.c of base Gunmel number Q.sub.B to impurity concentration N.sub.C of the collector region of the bipolar transistor lies within a range from 0.2.times.10.sup.-3 cm to 2.5.times..sup.-3 cm.

Semiconductor device having bipolar transistor with unique ratio of base

To enable a high speed operation and to increase the current gain, the disclosed a method of manufacturing a semiconductor device, comprising the steps of: forming a first semiconductor layer with a first-conductivity type in a semiconductor substrate; forming a second semiconductor layer with a second-conductivity type different from the first-conductivity type on the first semiconductor layer; insulation separating the formed second semiconductor layer into a first semiconductor region and a second semiconductor region by an insulating film; changing the second semiconductor region to the first-conductivity type; forming a pattern of an insulating film or a photoresist film having a hole at a partial area of the first semiconductor region of the semiconductor substrate; and implanting first-conductivity type impurities and second-conductivity type impurities at the first semiconductor region, respectively by use of the formed pattern as a mask, to form a first-conductivity type impurity region contacting with the first semiconductor layer and a second-conductivity type impurity region.

Method of manufacturing bimos device

A method of manufacturing a semiconductor device including selectively forming an element-isolating insulating layer on a surface of a semiconductor substrate to define active regions; forming a first insulating layer and removing respective portions thereof on surfaces of a second conductive type active region and a first active region of a first conductive type; oxidizing to form a gate oxide layer; forming and patterning a conductive layer to form a gate electrodes of MOS transistors and a base-extracting electrode of a bipolar transistor; forming an opening, in the base-extracting electrode, and a side wall insulating layer on an inner wall of the opening; removing first and second portions of the insulating layer to form an overhung portion; epitaxially growing a second conductive type semiconductor layer using the base-extracting electrode and active region of the first conductive type as a seed crystal; and selectively forming a first conductive type semiconductor layer that is to become an emitter that does not contact the base-extracting electrode.

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Yokohama, Japan

Kazumi Inoh