Hitachi, Ltd.

Renesas Electronics Corporation

Renesas Technology Corp.

Other

Floadia Corporation

Hitachi Ulsi Systems Co., Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi Ulsi Engineering Corp.

Hitachi Tohbu Semiconductor, Ltd.

Vlsi Engineering Corporation

Hitachi Usli Systems Co., Ltd.

Kazumasa Yanagisawa

Yusuke Kanno

Hiroyuki Mizuno

Takao Watanabe

Kazushige Ayukawa

Masanao Yamaoka

Hitoshi Tanaka

Yoshihiko Yasu

Kenichi Osada

Shoji Shukuri

Toshio Sasaki

Yasuhiro Taniguchi

Ryo Fujita

Katsuyuki Sato

Nobuhiro Oodaira

Tetsu Udagawa

Masakazu Aoki

Hideo Aoki

Goro Kitsukawa

Seiji Miura

Yuichiro Ishii

Eiichi Murakami

Takayuki Oshima

Hizuru Yamaguchi

Jun Satoh

Shinji Yoshida

Atsushi Miyanishi

Kazuyuki Tsunokuni

Kan Takeuchi

Kiyoshi Inoue

Koichiro Ishibashi

Toshihiro Tanaka

Yutaka Kobayashi

Kousuke Okuyama

Yutaka Shinagawa

Daisuke Okada

Yuji Tanaka

Shoji Yoshida

Kazufumi Suzukawa

Kosuke Okuyama

Yasuhiko Kawashima

Fukuo Owada

Eiichi Ishikawa

Yoshitaka Kinoshita

Takeshi Kataoka

Kyoko Ishii

Yasuto Igarashi

Takayuki Kawahara

Yasushi Takahashi

Hitoshi Miwa

Takashi Miyamoto

Toshio Yamada

Jun Sato

Masamichi Ishihara

Junichi Nishimoto

Atsushi Nozoe

Masayuki Nakamura

Tetsurou Matsumoto

Hiroshi Kawamoto

Takashi Shinoda

Shoji Wada

Takashi Kuraishi

Masashi Horiguchi

Takeshi Sakata

Kazuo Yano

Ryoichi Hori

Akihiko Takase

Kenichi Sakamoto

Toshio Sugano

Tomoyuki Ishii

Norihiko Moriwaki

Takashi Hayasaka

Naoki Kitai

Taro Osabe

Seiichiro Tsukui

Satoshi Oguchi

Bryan Atwood

Kiyoo Itoh

Yoshinobu Nakagome

Masayuki Miyazaki

Mitsuaki Katagiri

Yasushi Ishii

Michiaki Sugiyama

Atsushi Hiraishi

Toshifumi Takeda

Masaya Muranaka

Kentaro Saito

Koichi Toba

Goichi Ono

Takashi Miwa

Hideyuki Aoki

Satoshi Noda

Sadayuki Morita

Hiroyuki Miyazawa

Sadayuki Ohkuma

Yuri Azuma

Masafumi Onouchi

Kyoichiro Asayama

Seigoh Yukutake

Yoshihiro Shinozaki

The present invention provides a solid-state imaging device and a camera system capable of recording a still image without using a recording medium. Each pixel P of an image sensor is provided with a photodiode, a transfer transistor, a reset transistor, and an amplifying transistor, as well as a memory element that has functions of a select transistor. The memory element has a structure integrating a drain side select transistor, a source side select transistor, and a memory transistor. By applying a program voltage to a memory gate electrode as a gate voltage, the memory transistor stores charge of an amount corresponding to an amount of light received by the photodiode in a charge storage layer.

Solid-state imaging device and camera system

A non-volatile semiconductor memory device that achieves downsizing as compared to conventional cases is disclosed. A non-volatile semiconductor memory device has a configuration in which a memory cell is disposed between a programming bit line and a reading bit line. The reading bit line provided between adjacent memory cells is shared by the adjacent memory cells. This configuration of the non-volatile semiconductor memory device, in which the reading bit line is shared by the adjacent memory cells, leads to reduction of the number of reading bit lines as compared to that in a conventional configuration, and further leads to reduction of the area of a control circuit and a sense amplifier circuit connected with the reading bit line, thereby achieving downsizing as compared to conventional cases accordingly.

Nonvolatile semiconductor storage device

A multiply-accumulate operation apparatus is capable of sufficiently restraining a sneak current when employing a precharge method where the magnitude of an electric current flowing through an output line is detected. In a synapse operation section, memory cells storing respective synaptic connection weights are arranged in rows and columns. Output lines are connected to memory cells in the corresponding column, and input lines are connected to memory cells in the corresponding row. Each output line is precharged, and then its electric potential is decreased during the corresponding memory cells flow cell currents corresponding to their synaptic connection weights. A memory element of each memory cell includes a memory transistor, a drain side transistor, and a source side transistor connected in series, and is connected between the corresponding input and output line. The memory transistor stores a synaptic connection weight according to the amount of charge in a charge storage layer.

Multiplier-accumulator

When a memory cell (MC) is downsized by reducing the distance between a drain region () and a source region () on the surface of a fin (S) with a high impurity concentration inside the fin (S), the shape of the fin (S) can be set such that a potential difference between a memory gate electrode (MG) and the fin (S) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (MC) achieves downsizing and suppression of the occurrence of disturbance.

Memory cell, nonvolatile semiconductor storage device, and method for manufacturing nonvolatile semiconductor storage device

A memory cell includes a memory gate structure, a first select gate structure, and a second select gate structure. In the memory gate structure, a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a metal memory gate electrode are stacked in this order. The first select gate structure includes a metal first select gate electrode along a first sidewall spacer provided on a sidewall of the memory gate structure. The second select gate structure includes a metal second select gate electrode along a second sidewall spacer provided on another sidewall of the memory gate structure. Thus, the metal memory gate electrode, the metal first select gate electrode, and the metal second select gate electrode can be formed of a same metallic material as a metal logic gate electrode, permitting the memory cell to be formed together with the metal logic gate electrode.

Memory cell, semiconductor integrated circuit device, and method for manufacturing semiconductor integrated circuit device

A semiconductor device includes a first mode and a second mode different from the first mode, includes a memory circuit including a first switch, a memory array, and a peripheral circuit. A first power source line is electrically coupled with an I/O circuit of the peripheral circuit and is supplied with a first voltage in the first mode. A second power source line is electrically coupled with a memory cell of the memory array, and supplied with a second voltage lower than the first voltage in the second mode.

Semiconductor device

When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.

Semiconductor SRAM circuit having a plurality of MOSFETS controlling ground potential

A semiconductor device includes: a first power source line for supplying a first voltage; a second power source line for supplying a second voltage; a memory circuit coupled with the first and second power source lines; a first switch which electrically coupling the first power source line with the second power source line and electrically decoupling the first power source line from the second power source line, in response to a control signal; a second switch which electrically coupling the first power source line with the second power source line and electrically decoupling the first power source line from the second power source line, in response to the control signal, wherein a memory circuit includes a memory cell array and a peripheral circuit, wherein a memory cell array includes a plurality of memory cells, the memory cells coupled with the second power source line.

A semiconductor device including an active mode and a standby mode as operation modes, includes: a first power source line which accepts the supply of power in the active mode; a second power source line which accepts the supply of power in the active mode and the standby mode; a memory circuit to be coupled with the first and second power source lines; and a first switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The memory circuit includes a memory array to be coupled with the second power source line, a peripheral circuit to be coupled with the first power source line, and a second switch which electrically couples the first power source line with the second power source line.

A semiconductor integrated circuit device has a memory array including SRAM cells, a plurality of sense amplifiers for reading out data stored in the SRAM cells and a plurality of MOSFETS. The MOSFETs are controlled by a control signal to be in one of an active state or a standby state. Part of the MOSFETs are arranged along one end of the memory array and the other parts of the MOSFETs are arranged along another end of the memory array. The other end of the memory array is opposite to the one end of the memory array. The MOSFETs are controlled by the control signal to be turned ON in the active state and to be turned OFF in the standby mode.

Semiconductor memory device having a plurality of mosfets controlled to be in an active state or a standby state

A semiconductor device including a first N-type well and a second N-type well includes: a memory circuit to be coupled with first and second power source lines; and a first switch which electrically couples the first power source line with the second power source line and electrically decouples the first power source line from the second power source line. The memory circuit includes a memory array to be coupled with the second power source line, a peripheral circuit to be coupled with the first power source line, and a second switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The first and second switches each include a first PMOS transistor arranged in the first N-type well.

A semiconductor device includes a first power source line which accepts the supply of power in the active mode, a second power source line which accepts the supply of power in the active mode and the standby mode, a memory circuit to be coupled with the first and second power source lines and a first switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The memory circuit includes a memory array, a peripheral circuit and a second switch. Each of the first and second switches includes a first PMOS transistor and a second PMOS transistor.

To improve the electric performance and reliability of a semiconductor device. A memory gate electrode of a split gate type nonvolatile memory is a metal gate electrode formed from a stacked film of a metal filmand a silicon filmover the metal film. In an upper end part of the metal film, a metal oxide portionis formed by oxidation of a part of the metal film. A control gate electrode of the split gate type nonvolatile memory is a metal gate electrode formed from a stacked film of a metal filmand the silicon filmover the metal film

Semiconductor device and method of manufacturing the same

Growing community of inventors

Kokubunji, Japan

Kazumasa Yanagisawa