Kabushiki Kaisha Toshiba

Kazumasa Sunouchi

Akihiro Nitayama

Fumio Horiguchi

Katsuhiko Hieda

Takashi Yamada

Masami Aoki

Hiroshi Takato

Satoshi Inoue

Tohru Ozaki

Naoko Okabe

Mariko Habu

Fujio Masuoka

Takashi Ohsawa

Takeshi Hamamoto

Yoshiaki Asao

Yusuke Kohyama

Takeshi Kajiyama

Keiji Hosotani

Shinichi Watanabe

Satoshi Inaba

Keisuke Nakatsuka

Kentaro Nakajima

Takehiro Hasegawa

Shigeyoshi Watanabe

Motoyuki Sato

Tsuneaki Fuse

Yoshiyuki Shioyama

Kei Kurosawa

Akira Sudo

Yoichi Takegawa

Naoko Takenouchi

Seiichi Takedai

Thoru Ozaki

Satosi Inoue

Kouji Hasimoto

Tahru Ozaki

Kazushi Tsuda

According to one embodiment, a memory device includes a spin transfer torque magnetoresistive element including a first magnetic layer, a second magnetic layer, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer, a temperature detecting unit detecting an ambient temperature of the magnetoresistive element, and a write voltage generating unit generating a write voltage for the magnetoresistive element in accordance with the temperature detected by the temperature detecting unit.

Memory device

A semiconductor memory device includes a first magneto resistive element disposed in a memory cell portion, a first circuit disposed in the memory cell portion, the first circuit writing data into the first magneto resistive element or reading out data from the first magneto resistive element, and at least a portion of a second circuit disposed in a region below the memory cell portion.

Semiconductor memory device including memory cell portion and peripheral circuit portion

A semiconductor device is disclosed, which includes a semiconductor substrate, drain and source regions of a MOS transistor, a gate electrode formed on a surface of a channel region of the MOS transistor trench type element isolation regions in each of which an insulating film is formed on a surface of a trench formed in the surface of the semiconductor substrate, the element isolation regions sandwiching the channel region from opposite sides thereof in a channel width direction, and a conductive material layer for a back gate electrode, which is embedded in a trench of at least one of the element isolation regions, configured to be supplied with a predetermined voltage to make an depletion layer in a region of the semiconductor substrate under the channel region of the MOS transistor or to voltage-control the semiconductor substrate region.

Semiconductor device

A memory cell section includes a first wiring which is extended in a first direction, and a second wiring which is extended in a second direction different from the first direction, and a third wiring which is disposed between the first and second wirings, and a first magneto resistive effect element which is disposed at an intersection of the first and second wirings between the first and second wirings, and is connected to the second and third wirings. Further, a peripheral circuit section includes a fourth wiring, and a fifth wiring which is disposed above the fourth wiring, and a second magneto resistive effect element which is disposed between the fourth and fifth wirings and is connected to the fourth and fifth wirings to be used as a resistive element.

Semiconductor memory device using magneto resistive effect element

A gate electrode having a first insulating film laminated in the upper portion thereof is formed on a gate insulating film formed on a semiconductor substrate. A side wall is formed on the side wall of the gate electrode, and an insulating film is formed to cover the gate electrode and the side wall. Ion implantation is performed through the insulating film so that a diffusion layer is formed on the semiconductor substrate. An interlayer dielectric film is formed, and then the interlayer dielectric film and the insulating film are selectively etched so that an opening portion for exposing the gate insulating film is formed in a self-align manner with the gate electrode. Then, the gate insulating film in the bottom portion of the opening portion is removed so that the surface of the semiconductor substrate is exposed. Then, a wiring layer connected to the exposed surface of the semiconductor substrate is formed.

Semiconductor apparatus formed by SAC (self-aligned contact)

The present invention simplifies a manufacturing process by performing contact hole formation in a single step even in manufacturing a device having a self alignment contact. A cap layer having a contact portion is formed in a self alignment manner on a gate electrode formed on a silicon substrate. After a SiO,interlayer film is deposited on the cap layer and the silicon substrate, the patterning of a contact hole is performed. Thereafter, a wiring layer is formed in the contact hole. The diameter of the contact portion is formed differently from the diameter of the contact hole.

Semiconductor device with self-aligned contact and manufacturing method thereof

In a stack type memory cell of 8F,, bit line plug electrodes for connecting bit lines to source/drain diffusion layers of active regions in an area between two word lines WL are formed extend from the source/drain diffusion layers in parallel to the word lines WL and formed longer than the minimum element isolation width F and shorter than three times the minimum element isolation width F. Thus, a DRAM which uses stack type memory cells and whose integration density can be easily enhanced can be attained.

Semiconductor device with high integration density and improved performance

A semiconductor memory device includes a substrate, a first insulation layer formed on the substrate, a plurality of bit lines arranged on the first insulation layer, a second insulation layer formed all over the bit lines and having a plurality of first openings, an element isolating region formed on the second insulation layer, a plurality of island-like element forming semiconductor regions formed as surrounded by the element isolating region, a plurality of transistors respectively formed in the element forming semiconductor regions, and a plurality of capacitors respectively formed on the transistors. Each of the transistors includes a gate electrode insulatively formed on the element forming region, and a first and a second diffusion region formed on either side of the gate electrode, the first diffusion region being connected to a corresponding one of the bit lines through a via conductor formed in one of the first openings. Each of the capacitors has a storage electrode formed on the second diffusion region of each of the transistors.

Method for manufacturing semiconductor memory device

A semiconductor memory device comprises: a semiconductor substrate; a semiconductor region of a first conductive type formed in the semiconductor substrate; a diffusion region of a second conductive type different from the first conductive type, the diffusion region being formed on the surface of the semiconductor region; a trench formed in the semiconductor substrate so as to be adjacent to the diffusion region; a capacitor insulator film formed on a portion of a side surface of the trench, which extends from a position at a predetermined depth of the trench to a bottom portion of the trench, and on a bottom surface of the trench; a storage node formed so that a surface of the storage node buried in the trench has the same depth as that of the predetermined depth; a first insulator film formed in a portion of the side surface of the trench above the position of the predetermined depth of the trench, the first insulator having a window in a region contacting the diffusion region; and a storage node electrode formed on the storage node so as to bury the trench, the uppermost surface of a region of the storage node electrode contacting the diffusion region via the window being formed of a mono-crystalline silicon region. Thus, it is possible to improve the charge holding characteristic of a memory cell without deteriorating the performance of a cell transistor.

Semiconductor memory device and method for producing same

In a DRAM, a plurality of first MOSFETs are formed in a cell region on a semiconductor substrate based on the minimum design rule, and a first gate side-wall having a side-wall insulation film is formed on the side-wall portion of a first gate electrode of each of the first MOSFETs. At least one second MOSFET is formed in a peripheral circuit region on the semiconductor substrate, and a second gate side-wall having side-wall insulation films is formed on the side-wall portion of a second gate electrode of the second MOSFET. Both the first MOSFETs, which is capable of forming a fine contact hole self-aligned with the first gate electrode, and the second MOSFET, which is capable of sufficiently mitigating the parasitic resistance while suppressing the short channel effect, can be formed on the same substrate.

Semiconductor device and method for manufacturing the same

Semiconductor apparatus formed by SAC (self-aligned contact) method and

Semiconductor memory device and method for manufacturing the same

In a stack type memory cell of 8F.sup.2, bit line plug electrodes for connecting bit lines to source/drain diffusion layers of active regions in an area between two word lines WL are formed extend from the source/drain diffusion layers in parallel to the word lines WL and formed longer than the minimum element isolation width F and shorter than three times the minimum element isolation width F. Thus, a DRAM which uses stack type memory cells and whose integration density can be easily enhanced can be attained.

Semiconductor device with high integration density and improved

A dynamic RAM array comprises a substrate, a plurality of semiconductor island regions and a trench region formed on the substrate, each island region being surrounded by the trench region, and the trench region having wider trench portions and narrower trench portions, an insulating layer formed on the trench region, capacitors refilled in the wider trench portions, each capacitor having a plate electrode, a capacitor insulating layer and a storage node electrode, refilled layers formed in the narrower trench portion, for forming field isolation regions, MOS transistors formed on the island region, each MOS transistor having a source, a drain and a gate as word line, one of the source and drain being coupled with the storage node electrode, and bit lines perpendicular to the word line, being coupled with the other of the source and drain.

Dynamic RAM and method of manufacturing the same

In a DRAM having a structure in which a storage node electrode is formed via an insulator film in a trench formed in a memory cell region to thereby form a capacitor, and in which the storage node electrode is connected in the source/drain regions of a MOSFET through a storage node contact formed in a part of the insulator film, the trench is disposed so as to deviate widthwise in a channel region of the MOSFET, so that the distance between adjacent element regions is reduced without causing misalignment of masks used in the formation of the storage node contact, thereby to provide a miniaturized high-reliability DRAM. In addition, the storage node contact and the trench can be formed in large size.

Semiconductor memory device

Growing community of inventors

Yokohama, Japan

Kazumasa Sunouchi