Fujitsu Corporation

Vlsi Technology Research Association

Kazumasa Nawata

Yasunori Kanai

Toshiaki Sakai

Mitsuhisa Shimizu

Taichi Saitoh

Hiroki Yada

Hirokazu Suzuki

Eiji Sugiyama

Takayuki Tsuru

Kenichi Ohno

Tohru Hosomizu

Hiroyuki Tsunoi

Hisayosi Ooba

Satoru Sudo

A logic circuit in which first and second transistors are connected in series between high and low potential power sources with the middle point of the series connection used as the output terminal; A same- and inverse-phase signal generating unit is provided connected between the high and low potential power sources in parallel with the first and second transistors for generating same- and inverse-phase signals based on the single input signal output from the logic circuit. A transient signal generating unit is provided for generating transient large current signals at the rise time of the inverse-phase signals and generating transient cut-off signals at the fall time of the inverse-phase signals. The series connected first transistor is driven and controlled based on the regular-phase signals, while the second transistor is driven and controlled based on the transient large current signal and transient cut-off signal, thus producing an inverse-phase output by a simple circuit construction.

Logic circuit having sharper falling edge transition

A latch circuit including at least three gate circuits, and a noise resistance circuit. A first gate circuit (3, 4, 11, 16) receives a data signal (DT) and a clock signal (CLK). A second gate circuit (1, 7, 13, 17) is connected to an output of the first gate circuit. A third gate circuit (2, 5, 12 18) receives a first inverted clock signal (CLK) at an input terminal. A second input terminal of the third gate circuit is connected to an output of the second gate circuit and is a first output terminal is connected to an input terminal of the second gate circuit, so that a feedback line is formed between the second and third gate circuits. The noise resistance circuit (8, 9, 20, 21) has at least a signal delay element in the feedback line. The noise resistance circuit may include a filter circuit. The noise resistance circuit may also include an amplifier circuit.

ECL latch circuit having a noise resistance circuit in only one feedback

A semiconductor device such as an ECL gate array having emitter-follower-type output transistors, wherein protective elements are arranged between input/output pads and a power supply line connected to the collectors of the emitter-follower-type output transistors, whereby wiring between the protective elements and the power supply line become unnecessary so that the manufacturing process becomes easy and the integration degree is improved while a large tolerance voltage is maintained against destruction due to static electricity.

ECL gate array semiconductor device with protective elements

An ECL gate array comprising a plurality of basic cells. Each basic cell has a pair of emitter-coupled transistors, and a load connected between the collectors of the transistors and a power supply line. In accordance with a circuit design information, the resistance value of the load can be selected for increasing a noise margin of the output logic levels without deteriorating the switching speed.

ECL gate array with collector resistance compensation for distance from

An integrated circuit device having a simplified bias supply circuit for supplying bias power sources for a plurality of circuit units or cell units. The integrated circuit device cmprises: a cell unit array having a plurality of cell units disposed in a central portion of a semiconductor chip; a first power supply line and a second power supply line; and one or more common bias generating portions disposed at the periphery of the cell unit array, each of the common bias generating portions generating a single common bias voltage which differs from the potential of the second power supply line by a constant value. Each of the cell units comprises one or more logic circuit cells such as ECL type logic circuits, and an inner bias circuit which receives the common bias voltage and which generates a first inner bias voltage and a second inner bias voltage that are supplied to the respective logic circuit cell. The second inner bias voltage differs from the common bias voltage by a constant value, and the first inner bias voltage differs from the potential of the first power supply line at the cell unit by the value determined by the values of the elements in the inner bias circuit and by the common bias voltage.

Inner bias circuit for generating ECL bias voltages from a single common

A bias circuit for providing a reference voltage to an output circuit, for example, an ECL circuit in an LSI. The bias circuit is able to operate at a lower power supply voltage of about -2 V and includes a first transistor having an emitter which is connected to a power supply and a base and a collector commonly connected through an impedance circuit to ground. The bias circuit is also connected to the output circuit, whereby heat generation in the LSI is decreased.

Bias circuit with voltage and temperature compensation for an emitter

A method of manufacturing a semiconductor device for simultaneously forming a plurality of diffused regions of selectively different diffusion depths, comprises forming polycrystalline semiconductor layers of corresponding, selectively different depths on the semiconductor substrate surface provided with a diffusion mask having a plurality of diffusion windows. By the impurity diffusion into the substrate through the windows at the polycrystalline semiconductor layer interface with the substrate, a comparatively shallow diffused region and a comparatively deep diffused region are formed simultaneously by a single diffusion process, respectively, under the comparatively thick polycrystalline semiconductor layer and the comparatively thin polycrystalline semiconductor layer.

Method of manufacturing a semiconductor device

A large scale semiconductor integrated circuit device comprising plural transistors and resistors formed in one semiconductor substrate, and many emitter-coupled circuits formed by connecting the transistors and resistors with a double metallic layer on the substrate surface. Moreover, between the groups and respective input/output terminals, large scale transistors are provided for outputting the emitter-follower circuits. These groups containing the emitter coupled circuits are connected to the input/output terminals by the double metallic wiring layer.

Growing community of inventors

Kawasaki, Japan

Kazumasa Nawata