Sharp Kabushiki Kaisha Corporation

Kazumasa Kioi

Masayuki Natsumi

Masayoshi Koba

Nobuyoshi Kaiki

Akira Saito

Takae Sakai

Toshiaki Miyajima

Youji Kanie

Minoru Yoshioka

Mituo Matunami

Mamoru Okazaki

Atsushi Sakai

Tukasa Doi

This demodulation device receives and demodulates a digital broadcast wave. This demodulation device includes an RF search control unit () and a GI search control unit (). The RF search control unit () determines whether or not there is a broadcast wave in a certain channel, in accordance with an intensity of a signal outputted from a tuner () for receiving a digital broadcast wave. The GI search control unit () determines whether or not the broadcast wave is digital, based on whether or not the signal outputted from the tuner () contains a guard interval. Thus, the demodulation device is capable of efficiently searching for a channel containing a digital broadcast wave.

Demodulation device, demodulation device control method, demodulation device control program, and recording medium with recorded demodulation device control program

A digital demodulating apparatus comprises a tuner constituted by circuit elements to perform channel select processing to a signal; a demodulator that performs demodulation processing to a signal output from the tuner; a power supply unit that supplies a normal power to each circuit element, and supplies to the circuit element a test power different from the normal power, over a first time period in place of the normal power; a test noise measuring unit that measures the intensity of test noise contained in a signal to be output from the tuner, when the power supply unit supplies the test power over the first time period; a comparing unit that compares the intensity of the test noise measured by the test noise measuring unit with a noise reference value as a reference for updating of the normal power; and a power updating unit that updates the intensity of the normal power on the basis of a result of the comparison by the comparing unit.

Tuner, digital demodulating apparatus, controlling method of the apparatus, computer program product for the apparatus, recording medium recording thereon the product, and digital receiver

A MOS logic circuit is charged by adiabatic charging, and is composed of a clamp circuit having a pair of PMOS transistors, and two functional circuits, each having at least one NMOS transistor, a gate electrode of each of the NMOS transistors being an input node, one terminal of each functional circuit being connected to a common constant-voltage power source, and the other terminal of each functional circuit being connected to a drain electrode of the corresponding PMOS transistor, thus forming an output node. A substrate electrode of each of the NMOS transistors making up the two functional circuits is cross-connected to the output node of the other functional circuit. In this way, even in the HOLD operation, in which both input nodes fall to low level, the NMOS transistor which is to output low level becomes depletion mode, and the outputting operations are stabilized without increasing circuit size.

MOS logic circuit with hold operation

A switching circuit supplies a signal from a write memory selection terminal and its inverted signal to one of a first or a second selector and the other of the first or the second selector according to an output signal from a forward/backward translation selection terminal. In a forward translation process, the first and second selectors select a translated address on a translated address bus in a writing stage and select an input address on an input address bus in a reading stage. In a backward translation process, the selectors select the input address in the writing stage and select the translated address in the reading stage. Consequently, the forward translation and the backward translation are executed using the same translation table. An address translation table memory therefore stores therein only either a translation table for forward translation or a translation table for backward translation.

Sequential permutation apparatus for rearranging input data

An optically driven semiconductor device is disclosed which comprises a semiconductor substrate, a plurality of vertical field effect transistors formed on the substrate, and a plurality of optoelectric transducers formed on an insulating film above the respective transistors, wherein the transistors have the substrate in common as a drain. Also disclosed is an optically driven semiconductor device which comprises a semiconductor substrate, a vertical field effect transistor formed on the substrate and a solar cell formed on an insulating film above the substrate, wherein the solar cell is formed with a polycrystalline silicon layer or monocrystalline silicon layer grown by the chemical vapor deposition method. Moreover, there are disclosed optically coupled semiconductor relay devices using these optically driven semiconductor devices.

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Fujiidera, Japan

Kazumasa Kioi