Kabushiki Kaisha Toshiba

Kazumasa Ikeda

Kenji Shimoda

Seiichi Tanaka

Hisaharu Takeuchi

Shinji Yoda

Masaaki Kisou

Masatoshi Sumiyoshi

Hitoshi Kawabata

Naoki Mazda

Ken Hirata

A video signal processor, having an input receiving unit for selectively receiving either of a baseband video signal and a composite video signal are selectively input as an input video signal thereto, a H delay unit for delaying the selected input video signal by one line period ( H), an inter-line non-correlation component extractor for extracting inter-line non-correlation components between the input video signal and the H delay signal from the H delay unit, an inter-frame non-correlation component remover for removing inter-frame non-correlation components from the selected input video signal, a first subtractor responsive to the selection of the baseband video signal for subtracting the inter-line non-correlation component from the baseband video signal processed the inter-frame non-correlation component removal at the inter-frame non-correlation component removing means to result noise-reduced baseband video signals, a second subtractor responsive to the selection of the composite video signal the inter-line non-correlation component from the input composite video signal to result a first luminance signal, and a mixer for mixing a second luminance signal resulted from the inter-frame non-correlation component removal at the inter-frame non-correlation component remover with the first luminance signal from the second subtractor at a ratio defined by a motion signal to result a motion-adaptively processed luminance signal.

Video signal processor

A vertical impulse detecting circuit 104 detects the difference between a level of data of a present horizontal line of an input composite picture signal and a level of data of each of a horizontal line a plurality of lines ahead and a horizontal line a plurality of lines behind. Either an output signal of a three-line chrominance signal separating circuit 100 or an output signal of a horizontal chrominance signal separating circuit 101 is selected as a chrominance signal (CC) that is supplied to a subtracter 105 according to an output signal of the vertical impulse detecting circuit 104.

Luminance/chrominance separating circuit using predetermined separations

Image track display apparatus including a memory for delaying an image signal by at least one vertical scanning period, a first subtraction circuit for taking a first difference signal between the image signal and its delayed image signal through the memory. The first difference signal includes first and second polarity components, a non-linear processing circuit for multiplying the one polarity component of the first difference signal by K times (0&lt;K&lt;1) and for reducing the other polarity component of the first difference signal to the zero value when the other polarity component exceeds a prescribed value, a second subtraction circuit for taking a second difference signal between the output signal of the non-linear processing circuit and the image signal, and a display device for displaying the delayed image signal obtained through the memory circuit.

Image track display apparatus

Growing community of inventors

Kanagawa-ken, Japan

Kazumasa Ikeda