Kabushiki Kaisha Toshiba

Kazumasa Ando

Tomotaka Saito

Hideo Sakai

Akira Wada

Shingo Hanatani

Miki Sakai

Syoji Horie

An A/D converteris provided with analog input terminals, input terminal selection circuit, preset registers, preset data registers, preset data selection circuit, and sampling capacitor C. Input terminal selection circuitselects one of analog input terminals. Preset registersare correspondingly provided for analog input terminals. Preset data selection circuitselects preset digital data which preset data registersstores. Preset data stored at preset registerscorresponding to input terminalsdesignated by input terminal selection circuitare converted into analog signals as pre-charge voltages. One of the preset data is selected for each analog input terminalin response to kinds of the input voltages. It is supplied to sampling capacitor C as a pre-charge voltage for a sampling duration of a sampling period for the A/D conversion.

Analog-to-digital converter and microcomputer in which the same is installed

A programmable logic array comprises a PLA area having a plurality of banks wherein each of the bank has an array of a discharge typed logic circuit for decoding a micro-code, a command code is inputted to each bank every cycle for executing a predetermined command, and each bank outputs bank selection data for determining by which bank a command of a next cycle be decoded at the previous cycle, and a control circuit for selecting one bank for decoding the command code of the next cycle from the plurality of banks based on the bank selection data of each bank in the previous cycle, and for sending a command code to only the selected one bank to perform discharge of a discharge typed logic circuit, thereby stopping operations of other banks.

Programmable logic array having power-saving banks

A precharge transistor precharges a bus. A discharge transistor discharges the bus. A push-pull driver is connected to the bus, and consists of a p-channel MOS transistor and an n-channel MOS transistor. The push-pull driver sets the potential of the bus to 'H' level or 'L' level. A detection circuit detects which one of the discharge transistor and the push-pull driver is being driven. When the push-pull drive is being driven, a control circuit renders the precharge transistor inoperative.

Semiconductor integrated circuit

A transfer gate is made up of at least two p-channel MOS FETs and at least two n-channel MOS FETs. The current paths of the n-channel MOS FETs are connected in series, and the conduction of the FETs is controlled by a first control signal applied to the gates thereof. The current paths of the p-channel MOS FETs are also connected in series, and the conduction of the FETs is controlled by a second control signal applied to the gates thereof. The first and second control signals are opposite phase. The series circuit of the current paths of the p-channel FETs is connected in parallel to the series circuit of the current paths of the n-channel FETs. The p-channel FETs are formed in at least two n-type well regions, which is formed in the major surface region of a p-type semiconductor substrate at different locations separated from each other by predetermined distances.

Transfer gate with the improved cut-off characteristic

A noise cancelling circuit includes a delay circuit for delaying an input signal which is supplied to an input terminal, and a signal processing circuit responsive to the input signal and an output signal from the delay circuit, to generate an output signal corresponding to the input signal. The signal processing circuit has a first switching circuit, which includes first and second switching elements connected in series between a first power supply terminal and an output, and a second switching circuit, which includes third and fourth switching elements connected in series between a second power supply terminal and the output, wherein the first and third switching elements are responsive to the aforementioned input signal, by which they are set in mutually opposite conduction states, and the second and fourth switching elements are responsive to the output signal of the delay circuit, by which they too are set in mutually opposite conduction states.

Growing community of inventors

Kawasaki, Japan

Kazumasa Ando