Panasonic Intellectual Property Management Co., Ltd.

Nuvoton Technology Corporation Japan

Panasonic Semiconductor Solutions Co., Ltd.

Attaccato Limiied Liability Company

Kazuma Yoshida

Takeshi Watanabe

Ryosuke Okawa

Toshikazu Imai

Takeshi Imamura

Tsubasa Inoue

Yuichi Matsumoto

Eiji Yasuda

Shigetoshi Sota

Ryou Kato

Hirofumi Fujii

Kazuhiko Iwai

Masaaki Hirako

Yoshihiro Matsushima

Tetsurou Kakizawa

Marie Kuwahara

Mitsuaki Sakamoto

Yasuyuki Masumoto

Tomonari Oota

Kosuke Hosoi

Masaki Tamaru

Tetsuyuki Fukushima

Daisuke Ueta

Takashi Mukai

Yuta Ikeuchi

Michiya Otsuji

Taichi Sakamoto

Naoto Yamashita

Tomonari Ota

Dohwan Ahn

Daichi Iwanari

Kazuyoshi Tanaka

Hirofumi Fuji

A semiconductor device includes a first transistor disposed in a first region of a semiconductor layer and a second transistor disposed in a second region of the semiconductor layer, and includes, on the surface of the semiconductor layer, first source pads, a first gate pad, second source pads, and a second gate pad. In the plan view of the semiconductor layer, the first and second transistors are aligned in a first direction; the first gate pad is disposed such that none of the first source pads is disposed between the first gate pad and a side parallel to the first direction and located closest to the first gate pad; and the second gate pad is disposed such that none of the second source pads is disposed between the second gate pad and a side parallel to the first direction and located closest to the second gate pad.

Semiconductor device

Provided is a semiconductor device which is a facedown mounting, chip-size-package-type semiconductor device and includes: a transistor element including a first electrode, a second electrode, and a control electrode which controls a conduction state between the first electrode and the second electrode; a plurality of first resistor elements each including a first electrode and a second electrode, the first electrodes of the first resistor elements being electrically connected to the second electrode of the transistor element; one or more external resistance terminals to which the second electrodes of the plurality of first resistor elements are physically connected; a first external terminal electrically connected to the first electrode of the transistor element; and an external control terminal electrically connected to the control electrode. The one or more external resistance terminals, the first external terminal, and the external control terminal are external connection terminals provided on a surface of the semiconductor device.

To provide a negative electrode of a lithium ion battery excellent in cycle life characteristics. The negative electrode for a lithium ion battery includes an Si-based material as an active material, wherein a skeleton-forming agent including a silicate having a siloxane bond or a phosphate having an aluminophosphate bond as an ingredient is present on the surface and inside of an active material layer, and the skeleton of the active material is formed with the skeleton-forming agent.

Skeleton-forming agent and negative electrode using same

A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors. The thickness of the backside electrode ranges from 25 to 35 &#x3bc;m, and the ratio of the thickness of the backside electrode to the thickness of a semiconductor layer including the semiconductor substrate and the low-concentration impurity layer is 0.32 or more.

Semiconductor device, semiconductor module, and packaged semiconductor device

A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 &#x3bc;m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.

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Kyoto, Japan

Kazuma Yoshida