Nec Corporation

Bar-ilan University

Asahi Kasei Microdevices Corporation

Nec Corporation of America

Kazuma Ohara

Toshinori Araki

Jun Furukawa

Hikaru Tsuchida

Takuma Amada

Lindell Yehuda

Nof Ariel

Yuki Tanaka

Takao Takenouchi

Haruna Higo

Yuichi Miyahara

Joseph Keshet

Kazuya Kakizaki

Shir Aviv-Reuven

There is provided an integrator including: a first order delay unit which outputs an output signal obtained by delaying a signal in accordance with an input signal; a first feedback unit which generates a first feedback signal in accordance with the output signal; a second feedback unit which generates a second feedback signal in accordance with the output signal; an addition and subtraction unit which adds and subtracts the first feedback signal and the second feedback signal, respectively, to and from the input signal, for an input to the delay unit; and a control unit which causes the second feedback unit to operate as a delay circuit during the first period, and causes the second feedback unit to operate as a gain circuit having a gain smaller than 0 during the second period.

Integrator and delta-sigma modulator

The information processing apparatus comprises a basic operation seed storage part, a reshare value computation part, and a share construction part. The basic operation seed storage part stores a seed for generating a random number used when computation is performed on a share. The reshare value computation part generates a random number using the seed, computes a share reshare value using the generated random number, and transmits data regarding the generated random number to other apparatuses. The share construction part constructs a share for type conversion using the data regarding the generated random number and the share reshare value received from other apparatuses.

Information processing apparatus, secure computation method, and program

Provided is a delta-sigma modulator including a first integral unit configured to integrate an input analog signal, a second integral unit configured to integrate a signal output by the first integral unit, a quantizer configured to quantize a signal output by the second integral unit, a DA converter configured to perform DA conversion on an output of the quantizer and output a feedback signal to be fed back to the first integral unit, and a control unit configured to perform control to cause the first integral unit and the second integral unit to perform different integral operations during a first period and a second period, in which the second integral unit is configured to receive the feedback signal output by the DA converter via the first integral unit and integrate the feedback signal during the first period and the second period.

Delta-sigma modulator

In a secret computation system, each of the three or more secret computation servers is configured to transmit, to the auxiliary server, carry computation information for computing a carry indicating whether or not digit carry occurs when a share of arithmetic operation is added as a binary number. The auxiliary server is configured to compute the carry based on the carry computation information received and compute an adjustment value used for computing the share of the arithmetic operation from a share of logical operation by using the computed carry. The auxiliary server distributes the computed adjustment value to the three or more secret computation servers. Each of the three or more secret computation servers is configured to convert the share of the logical operation to the share of the arithmetic operation by using a distributed value of the adjustment value.

Secret computation system, secret computation server, auxiliary server, secret computation method, and program

A verification apparatus acquires a source code for multiparty computation, while changing a combination of options settable to a multiparty computation compiler, compiles the source code for each combination of options to generate a plurality of multiparty computation executable codes, selects at least one multiparty computation executable code from the plurality of multiparty computation executable codes as a verification code and provides the at least one verification code to a verification environment of multiparty computation, generates an evaluation index with respect to an execution result of at least one verification code in the verification environment, and selects at least one recommended code from the plurality of multiparty computation executable codes, based on the evaluation index corresponding to at least one verification code and outputs the selected recommended code.

Verification apparatus, multiparty computation verification system, and method and program for verifying multiparty computation executable code

An information processing apparatus comprises a partial modular exponentiation calculating part and a partial modular exponentiation synthesizing part. The partial modular exponentiation calculating part is given a base in plaintext and a modulo in plaintext and shared exponents and calculates a partial modular exponentiation that equals a set of shared values according to a modular exponentiation of the base raised by the shared exponent. The partial modular exponentiation synthesizing part calculates shared values of the modular exponentiation from the partial modular exponentiation that equals shared values relating to the modular exponentiation of a sum of shared exponents.

When an absolute value of a difference value between a first share and a second share which are secret-shared is less than or equal to a natural number t, the information processing apparatus calculates the difference value between the first share and the second share. Furthermore, the information processing apparatus performs a comparison in magnitude of the first share and the second share using bit-decomposition from a least significant bit to an m-th bit (m being a natural number) of the difference value.

Information processing apparatus, secret calculation method, and program

The present invention provides a bit decomposition secure computation system comprising: a share value storage apparatus to store share values obtained by applying (2, 3) type RSS using modulo of power of 2 arithmetic; a decomposed share value storage apparatus to store a sequence of share values obtained by applying (2, 3) type RSS using modulo 2 arithmetic; and a bit decomposition secure computation apparatus that, with respect to sharing of a value w, r1, r2, and r3 satisfying w=r1+r2+r3 mod 2{circumflex over (&#x2003;)}n, where {circumflex over (&#x2003;)} is a power operator and n is a preset positive integer, being used as share information by the (2, 3) type RSS stored in the share value storage apparatus, includes: an addition sharing unit that sums two values out of r1, r2 and r3 by modulo 2{circumflex over (&#x2003;)}n, generates and distributes a share value of the (2, 3) type RSS with respect to the sum; and a full adder secure computation unit that executes addition processing of the value generated by the addition sharing unit and a value not used by the addition sharing unit, for each digit, by using secure computation of a full adder, and stores the result in the decomposed share value storage apparatus.

Bit decomposition secure computation apparatus, bit combining secure computation apparatus, method and program

This numerical splitting device: acquires a numerical value w and a parameter p; generates a first random number r1 and a second random number r2; computes a third random number r3 based on the numerical value w, parameter p, first random number r1, and second random number r2 according to an expression, r3=w&#x2212;r1-r2 mod p; computes first to third segments s1, s2, s3 based on the first to third random numbers r1, r2, r3 and the parameter p according to expressions, s1=r1+r2 mod p, s2=r2+r3 mod p, and s3=r3+r1 mod p; and transmits a pair of the first segment s1 and the second random number r2, a pair of the second segment s2 and the third random number r3, and a pair of the third segment s3 and the first random number r1 to first to third secure computation devices, respectively.

Numerical splitting device, transmission information generating device, secure computation device, method, program recording medium, and secure computation system

There is provided a conversion apparatus with which a secure computation execution environment may be easily constructed. The conversion apparatus comprises an input part and a conversion part. The input part inputs a source code. The conversion part converts the input source code so that a secure computation compiler processes it based on setting information relating to secret computation executed by a plurality of secure computation servers.

Conversion apparatus, conversion method and program

A bit-decomposition secure computation apparatus uses r1, r2, and r3 satisfying w=r1+r2+r3 mod 2{circumflex over (&#x2003;)}n as share information of (2, 3) threshold type RSS (Replicated Secret Sharing) stored in a share value storage apparatus, and includes an addition sharing part that sums two values out of the share information by modulo 2{circumflex over (&#x2003;)}n arithmetic and distributes the sum using (2, 3) type RSS; and a full adder secure computation part that adds the value generated by the addition sharing part by distributing the sum of the two values to share information of one remaining value other than the two values used by the addition sharing part for each digit by using secure computation of a full adder.

Secure computation apparatus, system, method and program

A method for multiparty computation wherein a plurality of parties each compute a preset function without revealing inputs thereof to others, comprises: each of the parties performing a validation step to validate that computation of the function is carried out correctly, wherein the validation step includes: a first step that prepares a plurality of verified multiplication triples and feeds a multiplication triple to a second step when required; and the second step that consumes a randomly selected multiplication triple generated by the first step, wherein the first step performs shuffling of the generated multiplication triples, in at least one of shuffle in a sequence and shuffle of sequences.

Multiparty computation method, apparatus and program

There is provided a system for computing a secure statistical classifier, comprising: at least one hardware processor executing a code for: accessing code instructions of an untrained statistical classifier, accessing a training dataset, accessing a plurality of cryptographic keys, creating a plurality of instances of the untrained statistical classifier, creating a plurality of trained sub-classifiers by training each of the plurality of instances of the untrained statistical classifier by iteratively adjusting adjustable classification parameters of the respective instance of the untrained statistical classifier according to a portion of the training data serving as input and a corresponding ground truth label, and at least one unique cryptographic key of the plurality of cryptographic keys, wherein the adjustable classification parameters of each trained sub-classifier have unique values computed according to corresponding at least one unique cryptographic key, and providing the statistical classifier, wherein the statistical classifier includes the plurality of trained sub-classifiers.

Systems and methods for generating and applying a secure statistical classifier

A random number generation server device includes a random number generation unit generating random numbers, a share addition unit generating secret shared data masked using random numbers and the secret shared data of operands in secret equality determination, a secret shared data generation unit generating secret shared data of inputted values, a secret shared data restoration unit obtaining the original values by restoring the secret shared data, and a determination bit-conjunction unit using the secret shared data to perform secret equality determination. A mask value restoration server device includes a secret shared data generation unit, a secret shared data restoration unit, and a determination bit-conjunction unit. A secure computation server device includes a secret shared data generation unit, a secret shared data restoration unit, and a determination bit-conjunction unit.

Secret equality determination system, secret equality determination method and secret equality determination program recording medium

A server device, a secret equality determination system, a secret equality determination method and a secret equality determination program recording medium are provided which, regardless of the server sharing scheme, can run with no difference in the number of communication rounds, whether carried out with a ring of order 2 or with a ring of an order greater than 2. This server device is provided with a secret shared data generation unit, a data storage unit, a mask unit, a random number share bit-conjunction unit, a random number share generation unit, a determination bit-conjunction unit and a secret shared data restoration unit. The secret shared data generation unit generates secret shared data. The data storage unit stores the secret shared data. The mask unit uses random number secret shared data to mask certain shared data. The random number share generation unit generates random number shares in which random numbers are secretly shared. In parallel with other calculations, the random number share bit-conjunction unit calculates the logical product of the values in which the random numbers are secretly shared. The determination bit-conjunction unit performs a secret equality determination using the value outputted by the random number share bit-conjunction unit.

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Tokyo, Japan

Kazuma Ohara