Nec Corporation

Renesas Electronics Corporation

Nec Electronics Corporation

Kazuki Yokota

Toshiyuki Hirota

Masanobu Zenke

Tomomi Kurokawa

In an element isolation region defining an element formation region, there is formed an element isolation unit including an element isolation unit and the other element isolation unit. The other element isolation unit is arranged in a direction intersecting a direction in which the element isolation unit extends from the element isolation unit. The element isolation unit includes a sidewall oxide film formed in a trench, a titanium film, a titanium nitride film, and a tungsten film. The tungsten film is formed to cover the bottom surface of a trench in the element isolation unit and to close an opening end of a trench in the other element isolation unit. A plug is formed in contact with the tungsten film of the element isolation unit.

Semiconductor device and its manufacturing method

A photoresist is exposed to light under a condition that sensitivity of a second portion of the photoresist on a recessed portion of a base layer is higher than sensitivity of a first portion of the photoresist on a projecting portion of the base layer.

Semiconductor device and method for manufacturing the same

The present invention relates to an overlay mark used for the measurement of the overlay accuracy between layered patterns and alignment at the time of exposure; which has a grooved pattern surrounding a mark pattern that is formed by engraving a groove or an indent in a prescribed position on a layer where a circuit pattern is formed so as to protect this mark pattern from being deformed by thermal expansion or contraction of this layer. The present invention enables to form a multi-layered circuit pattern with a high accuracy and a high yield in production, even in the formation of a minute and densely-spaced circuit pattern.

Overlay mark, method of measuring overlay accuracy, method of making alignment and semiconductor device therewith

An alignment mark set is provided, which facilitates the formation of a desired contour of each alignment mark and which suppresses the degradation of measurement accuracy for alignment of patterns. This alignment mark set comprises: (a) a first alignment mark formed in an exposure area; the area having a periphery, first central axis, and a second central axis perpendicular to the first axis; the first alignment mark being located near the first central axis and apart from the second axis; (b) a second alignment mark formed in the exposure area; the second alignment mark being located near the second central axis and apart from the first axis; and (c) when the exposure areas are regularly arranged in such a way as to have a same orientation in a plane, each of the first and second alignment marks in one of the sets is not located close to the first and second alignment marks in another of the sets, thereby ensuring irradiation of exposing light to all the areas. It is preferred that each of the first and second marks is square.

Alignment mark set and method of measuring alignment accuracy

A reticle has a main pattern to be transferred to a photo-sensitive layer and surrounded by a non-transparent layer, and a discriminative pattern loops in the non-transparent layer so as to define an area to be inspected for serious defects, wherein the discriminative pattern is implemented by plural non-transparent portions such as strips arranged at intervals less than the minimum width to be transferred at the maximum resolution of the reduction projection aligner; however, the discriminative pattern or the plural non-transparent portions occupy a looped area wider than a minimum width to be recognized by a pattern recognition system so that the discriminative pattern clearly defines the area to be inspected regardless of the resolution.

Reticle having discriminative pattern narrower in pitch than the minimum pattern width but wider than minimum width in the pattern recognition

In a method for forming an annular-shaped and vertically extending bottom electrode of a memory cell capacitor, a conductive film is formed on an inter-layer insulator. A photo-resist material is applied on the conductive film to form a photo-resist film thereon. The photo-resist film is patterned by a photo-lithography using a mask which includes a transparent plate-like body and a phase shifting film selectively provided on a predetermined region of the transparent plate-like body to form an annular-shaped and vertically extending photo-resist pattern over the conductive film. The conductive film is subjected to an anisotropic etching, in which the annular-shaped and vertically extending photo-resist pattern is used as a mask, to form an annular-shaped and vertically extending bottom electrode under the annular-shaped and vertically extending photo-resist pattern. The annular-shaped and vertically extending photo-resist pattern is removed.

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Tokyo, Japan

Kazuki Yokota