Winbond Electronics Corporation

Spansion Llc.

Kazuki Yamauchi

Kenji Arai

Junya Kawamata

Tsutomu Nakai

Hirokazu Nagashima

Kenichi Takehana

Hiroki Murakami

Makoto Senoo

Katsutoshi Suito

Naoaki Sudo

Kazuhide Kurosaki

Oron Michael

Jongjun Kim

Youn-Cherl Shin

The disclosure prevents inconsistencies in a busy state between a master side memory chip and a slave side memory chip during a reset operation. A flash memory device () of the disclosure includes a master side memory chip () and at least one slave side memory chip (). A controller () of the master side memory chip () selects the master side memory chip or the slave side memory chip based on an externally inputted address, and performs a reset of the selected memory chip when a reset command is inputted. The data read from a specific area of a memory cell array of the master side memory chip is set in a register. The controller () controls a readout of the reset in a manner that time required for setting the data of the register is longer than time required for the reset of the selected memory chip.

Semiconductor memory device and reset method thereof

An NAND flash memory and a reading method thereof capable of high-speed reading of SFDP data are provided. The flash memory includes a memory cell array, a page buffer/reading circuitand a controller. The page buffer/reading circuitincludes a first latch circuit Land a second latch circuit L. The first latch circuit Lkeeps data read from the memory cell array. The second latch circuit Lkeeps data transferred from the first latch circuit L. Just after power is turned on or reset, the controllercontrols data of block/pageof the memory cell array to be kept in the second latch circuit Land controls the SFDP data to be kept in the first latch circuit L. The SFDP data or the data of block/pageis serially output according to an input command.

NAND flash memory and reading method thereof

A semiconductor memory device which is able to perform a power sequence with high reliability is provided. When a power from an external device is supplied, the controller of the flash memory of the invention is configured to read codes stored in a read-only memory in synchronization with a clock signal to perform a power-on sequence. In addition, the controller is further configured to deactivate the clock signal so as to pause the power-on sequence when it has been detected during the power-on sequence that the voltage of the power is not greater than a threshold, and to activate the clock signal to resume the power-on sequence when it is detected that the voltage of the supplied power exceeds the threshold again.

Semiconductor memory device and methods for operating a semiconductor memory device

A semiconductor memory device preventing inconsistent busy states between a plurality of memory chips is provided. A semiconductor memory device includes a master chip and at least one slave chip. The master chip and the slave chip include a status register capable of storing protection information. When a write-protect (WP) commend for locking the protection information of the status register is input, the protection information and lock information are programmed in a memory array. At this time, programming is controlled in a manner that a programming time in a selected memory chip is longer than a programming time in an unselected memory chip.

Semiconductor storage device

A semiconductor storage device with a smaller chip size than prior art and a readout method are provided. The semiconductor storage device includes a memory cell array; a page buffer/sense circuit having a sensing node for sensing readout data from a selected page of the memory cell array and a latch circuit for holding data sensed by the sensing node; and a controller controls operations on the memory cell array. The sensing node includes an NMOS capacitor.

Semiconductor storage device and readout method thereof

A semiconductor memory device is provided to keep data reliability while decreasing programming time. A NAND flash memory loads programming data from an external input/output terminal to a page buffer/sense circuit. A detecting circuit for monitoring the programming data detects whether the programming data is a specific bit string. If it is detected that the programming data is not a specific bit string, a transferring/writing circuit transfers the programming data kept by the page buffer/sense circuit to an error checking correction (ECC) circuit, and an ECC code generated by an ECC operation is written to the page buffer/sense circuit. If it is detected that the programming data is a specific bit string, transfer of the programming data kept by the page buffer/sense circuit is forbidden and a known ECC code corresponding to the specific bit string is written to the page buffer/sense circuit.

Semiconductor memory device and programming method thereof

The invention provides a semiconductor memory device and a reading method thereof, which are capable of suppressing a peak current when pre-charging a bit line are provided. The reading method of a flash memory of the present invention includes steps of: pre-charging a selected bit line; and reading a voltage or a current of the pre-charged selected bit line. The step of pre-charging is performed by pre-charging a sense node SNS to Vcc&#x2212;Vth at a time t, pre-charging a node TOBL to VCLAMPat a time t, pre-charging the node TOBL to VCLAMPat a time t, and pre-charging the sense node SNS to Vcc at a time t

Semiconductor memory device and reading method thereof

The invention provides a semiconductor memory device capable of maintaining data reliability and shortening programming time. A flash memory of the invention includes a memory array, a page buffer/sensor circuit, an input/output bufferconnected to an external input/output terminal, and an ECC circuitfor checking and correcting data errors. In a programming operation, the input/output bufferloads programming data into the page buffer/sensor circuitand the ECC circuitin parallel. The ECC circuitwrites parity bits generated from ECC calculation into a spare domain of the page buffer/sensor circuit. After the ECC procedure, the data held by the page buffer/sensor circuitare programmed to a selected page.

Semiconductor memory device and programming method of NAND flash memory

A semiconductor memory device, an erasing method and a programming method are provided. The semiconductor memory device includes a memory array, which includes a plurality of NAND strings; a page buffer/sensing circuit, which is connected to the NAND strings of the memory array through bit lines and outputs whether the NAND strings include failures; and a detecting circuit, which is connected to the plurality of page buffer/sensing circuits and detects a number of the failures among the NAND strings of a selected block. The block is determined to be usable when the number of the failures among the NAND strings detected by the detecting circuit is less than or equal to a fixed number, and the block is determined to be unusable as a bad block when the number of the failures exceeds the fixed number.

Semiconductor memory device, erasing method and programing method thereof

A non-volatile semiconductor memory device is provided. A determination circuitused to determine the suspected qualification is connected with a plurality of page buffer/sensing circuitsvia wirings PB_UP, PB_MG, PB_DIS. The page buffer/sensing circuitincludes a transistor Qin which a reference current Iref flows through a transistor Qwhen the programming verification is unqualified. The determination circuitincludes a comparator CMP, a voltage of the wiring PB_UP is supplied to one of input terminals of the comparator CMP, and a reference voltage Vref is supplied to another one of the input terminals. The reference voltage Vref is generated by a reference current (Iref*N) whose amount is corresponding to an unqualified bit number (N) which is determined to be suspectedly qualified.

Non-volatile semiconductor memory device

A non-volatile semiconductor memory includes a memory array, a selecting device selecting a page according to addresses, a data storage device, storing page data, and an output device outputting the stored data. The data storage device includes a first data storage device receiving data from a selected page of the memory array, a second data storage device receiving data from the first data storage device, and a data transmission device configured between the first and the second data storage device. The data transmission device transmits data in a second part of the first data storage device to the second data storage device when data in a first part of the second data storage device is output, and transmits data in a first part of the first data storage device to the second data storage device when data in a second part of the second data storage device is output.

Non-volatile semiconductor memory data reading method thereof

A semiconductor device includes a first nonvolatile storage area including a plurality of sectors, a second nonvolatile storage area, a third nonvolatile storage area located in the first nonvolatile storage area, a fourth nonvolatile storage area located in the second nonvolatile storage area, and a control portion selecting one of a first mode and a second mode. In first mode, sectors where the third nonvolatile storage area is not located in the first nonvolatile storage area are used as a main storage area, and the second nonvolatile storage area is used to store a program or data that is read before the first nonvolatile storage area is accessed, the third nonvolatile storage area being used to store control information that controls writing, reading, and erasing of data involved in the first nonvolatile storage area or the second nonvolatile storage area. In the second mode, the first nonvolatile storage area is used as the main storage area, and the fourth nonvolatile storage area is used to store the control information.

Semiconductor device and method for controlling thereof

A semiconductor device has a plurality of bit lines BL provided in a memory cell area, a plurality of word lines WL provided crossing the plurality of bit lines BL, a plurality of diffusion source lines VSL provided along the plurality of word lines WL, a plurality of non-volatile active cells AC storing data, the plurality of non-volatile active cells AC being provided at cross sections of the plurality of bit lines BL and the plurality of word lines WL and being connected to the plurality of bit lines BL, the plurality of word lines WL, and the plurality of diffusion source lines VSL, and a controller simultaneously writes or reads data to and from at least two active cells AC among the plurality of active cells AC, in which the number of the plurality of active cells AC is less than that of the cross sections.

Semiconductor device and controlling method for the same

Structures, methods, and systems for enhanced erasing operation for non-volatile memory are disclosed. In one embodiment, a semiconductor device which comprises a memory cell array having a plurality of non-volatile memory cells, a negative voltage generating circuit for applying a negative voltage to a word line of the memory cell array during an erasing operation of the memory cell array, and a positive voltage generating circuit for applying a positive voltage to a well of the memory cell array when the negative voltage reaches a predetermined voltage.

Growing community of inventors

Kanagawa, Japan

Kazuki Yamauchi