Cornell University

University of Notre Dame Du Lac

Kazuki Nomoto

Debdeep Jena

Zongyang Hu

Huili Grace Xing

Wenshen Li

Grace Huili Xing

Shyam Bharadwaj

Vladimir Protasenko

Huili (Grace) Xing

Bo Song

Henryk Turski

Mingda Zhu

Alexander Austin Chaney

Austin Hickman

Len Van Deurzen

Kevin Lee

A method for achieving voltage-controlled gate-modulated light emission using monolithic integration of fin- and nanowire- n-i-n vertical FETs with bottom-tunnel junction planar InGaN LEDs is described. This method takes advantage of the improved performance of bottom-tunnel junction LEDs over their top-tunnel junction counterparts, while allowing for strong gate control on a low-cross-sectional area fin or wire without sacrificing LED active area as in lateral integration designs. Electrical modulation of 5 orders, and an order of magnitude of optical modulation are achieved in the device.

Bottom tunnel junction light-emitting field-effect transistors

A vertical gallium oxide (Ga2O3) device having a substrate, an n-type GaOdrift layer on the substrate, an, n-type semiconducting channel extending from the n-type GaOdrift layer, the channel being one of fin-shaped or nanowire shaped, an n-type source layer disposed on the channel; the source layer has a higher doping concentration than the channel, a first dielectric layer on the n-type Ga2O3 drift layer and on sidewalls of the n-type semiconducting channel, a conductive gate layer deposited on the first dielectric layer and insulated from the n-type source layer, n-type semiconducting channel as well as n-type Ga2O3 drift layer, a second dielectric layer deposited over the conductive gate layer, covering completely the conductive gate layer on channel sidewalls and an ohmic source contact deposited over the n-type source layer and over at least a part of the second dielectric layer; the source contact being configured not to be in electrical contact with the conductive gate layer.

Vertical gallium oxide (GA2O3) power FETs

Described herein are the design and fabrication of Group III trioxides, such as β-GaO, trench-MOS barrier Schottky (TMBS) structures with high voltage (>1 kV), low leakage capabilities, while addressing on the necessary methods to meet the requirements unique to Group III trioxides, such as β-GaO.

High voltage gallium oxide (GaO) trench MOS barrier schottky and methods of fabricating same

A device that includes a metal(III)-polar III-nitride substrate having a first surface opposite a second surface, a tunnel junction formed on one of the first surface or a buffer layer disposed on the first surface, a p-type III-nitride layer formed directly on the tunnel junction, and a number of material layers; a first material layer formed on the p-type III-nitride layer, each subsequent layer disposed on a preceding layer, where one layer from the number of material layers is patterned into a structure, that one layer being a III-nitride layer. Methods for forming the device are also disclosed.

Platforms enabled by buried tunnel junction for integrated photonic and electronic systems

A nitride-based field effect transistor (FET) comprises a compositionally graded and polarization induced doped p-layer underlying at least one gate contact and a compositionally graded and doped n-channel underlying a source contact. The n-channel is converted from the p-layer to the n-channel by ion implantation, a buffer underlies the doped p-layer and the n-channel, and a drain underlies the buffer.

Polarization induced doped transistor

Growing community of inventors

Notre Dame, IN, United States of America

Kazuki Nomoto