Sandisk Technologies Inc.

Kazuki Isozumi

Masanori Tsutsumi

Shinsuke Yada

Naohiro Hosoda

Parth Amin

Genta Mizuno

Yusuke Mukae

Ryo Nakamura

Yu Ueda

Shuichi Hamaguchi

Xiang Yang

Jiahui Yuan

Huai-Yuan Tseng

Yu-Chung Lien

Abhijith Prakash

Anubhav Khandelwal

Sayako Nagamine

Keyur Payak

To address neighbor select gate interference between neighboring NAND block sub-divisions when one sub-division is program selected and its neighbor is un-selected, a biasing scheme for the GIDL select gates is introduced to reduce such disturbs. In a three-dimensional NAND memory with a sub-division structure and with two drain side GIDL select gate layers, when a sub-division is program selected and its neighboring sub-division is un-selected, the upper of the two drain side GIDL select gate layers is biased to a first voltage for all of the sub-divisions, while for the lower drain side GIDL select gate layer the gates are biased to be off for the un-selected sub-divisions and biased at a second voltage for the selected sub-division, where the second voltage is configured to turn on the lower drain side GIDL select gates and the first voltage is of a higher level than the second voltage.

Select gate bias gradation structure in NAND memory

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.

Three-dimensional memory device containing amorphous and crystalline blocking dielectric layers

The following disclosure is directed to mitigating issues related to semi-circle drain side select gate (SC-SGD) memory holes in memory structures. When a memory hole is cut, the channel and the charge trap layer of the memory hole cut. Further, the outer dielectric layer (used to shield the channel and the charge trap layer) is cut and partially removed. When the selected SC-SGD is selected for an operation (e.g., programming), the channel and the charge trap layer are exposed to neighboring electrical field from bias voltage applied to an unselected SC-SGD. To prevent or mitigate the effects of this electrical field, a negative bias voltage is applied to the unselected SC-SGD. Additionally, this disclosure is directed to self-compensating techniques for SC-SGD. For example, the memory structure can utilize the neighboring electric field during verify, program, and read operations, whether the neighboring electric field is relatively strong or weak.

Systems and methods for adjusting threshold voltage distribution due to semi-circle SGD

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, first memory opening fill structures extending through the alternating stack and including a respective first vertical semiconductor channel having a tubular section and a semi-tubular section, second memory opening fill structures, first bit lines electrically connected to a respective subset of the first drain regions, second bit lines electrically connected to a respective subset of the second drain regions, and an erase voltage application circuit configured to electrically bias the first bit lines at a first bit line erase voltage and the second bit lines at a second bit line erase voltage during an erase operation. The first bit line erase voltage is greater than the second bit line erase voltage.

Three dimensional memory device containing truncated channels and method of operating the same with different erase voltages for different bit lines

Apparatus and methods are described to reduce program disturb for a memory string with a partial select gate drain, which is partially cut by a shallow trench. The memory string with a partial select gate drain is linked with a neighboring full select gate drain that during its programming can cause a program disturb in the memory string with a partial select gate drain. The bias voltage applied to the selected full select gate drain can be controlled from a high state for low memory program states to a lower state for the high memory program states. The high data states may cause program disturb. The reduction in the bias voltage can match a reduction in the bias voltage applied to the bit lines to reduce the program disturb while providing adequate signal to program the high states on the memory string of the full select gate drain.

System and methods for programming nonvolatile memory having partial select gate drains

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Yokkaichi, Japan

Kazuki Isozumi