Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Kazuhito Tsutsumi

Hirotada Kuriyama

Shigenobu Maeda

Shigeto Maegawa

Yoshiyuki Ishigaki

Toshiaki Iwamatsu

Takashi Ipposhi

Toshiaki Tsutsumi

Motomu Ukita

Il-Jung Kim

Motoi Ashida

Yasuo Inoue

Tadashi Nishimura

Yuuichi Hirano

Hideaki Nagaoka

Tatsuhiko Akiyama

Yutaka Arita

Yoshikazu Kamitani

Eiji Hamasuna

Tadafumi Kishimoto

Yoshiyuki Haraguti

Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (), a channel () and a source () are integrally formed on a surface of a second oxide film () by polysilicon. The drain () is formed to be connected with a pad layer () (second polycrystalline semiconductor layer) through a contact hole () which is formed to reach an upper surface of the pad layer (). The pad layer () positioned on a bottom portion of the contact hole () (opening) is provided with a boron implantation region BR.

Thin-film transistor and method of fabricating the same

In a semiconductor device, a first conductive layer ( ) is located on a semiconductor substrate ( ) through an insulating film ( ) and beneath a first insulating layer ( ). On the first insulating layer ( ) is formed a second conductive layer ( ) followed by a second insulating layer ( ), either or both of which are very thin. A third conductive layer ( ) is placed on the second insulating layer ( ). A connecting column ( ) extends from the third conducting layer ( ) through and forming an end contact with the second conductive layer ( ) to the first conducting layer ( ) and the substrate ( ), with a greater portion of the column resting upon the substrate ( ). The third conductive layer ( ) forms the gate electrode ( ) of a top gate type TFT.

Semiconductor device

A semiconductor device for CSP mounting which avoids errors due to alpha rays and is highly stress-resistant is provided. A buried oxide film ( ) is formed on a semiconductor substrate ( ), and a MOS transistor having an SOI structure is formed on the buried oxide film ( ). The MOS transistor comprises source and drain regions ( ) formed in a semiconductor layer ( ), and a gate electrode ( ). An aluminum pad ( ) connected to any one of the source and drain regions ( ) through a connecting mechanism not shown, and a silicon nitride film ( ) having an opening on the top of the aluminum pad ( ) are formed on an interlayer insulation film ( ). A layer of titanium ( ) and a layer of nickel ( ) are formed extending from the aluminum pad ( ) to an end of the silicon nitride film ( ). A solder bump ( ) is disposed on the layer of nickel ( ).

SOI based transistor inside an insulation layer with conductive bump on the insulation layer

A boron nitride inclusion sheet is applied on the surface of a mold package enclosing a semiconductor chip so as to prevent soft error caused by a thermal neutron.

Semiconductor device including thermal neutron absorption material

A shared contact is provided on the side of a drain active region of each of two load transistors. Thus, a stabilized low voltage operation is ensured in a full CMOS type SRAM memory cell having the shared contact.

Static semiconductor memory device

An SRAM is provided in which adjacent contact holes cannot be connected and which can be miniaturized. An SRAM memory cell includes a gate electrode formed on a silicon substrate, and an interlayer insulation film covering the gate electrode. The interlayer insulation film has a contact hole which reaches an active region and a contact hole which reaches the gate electrode. The contact holes are positioned almost in a lattice manner.

A thin film transistor has a gate electrode formed of polysilicon on a surface of an insulating substrate or an insulating layer. The surface of the gate electrode is covered with a dielectric layer. A polysilicon layer is formed on a surface of the dielectric layer and source/drain regions are formed in this polysilicon layer. The dielectric layer covers the surface of the gate electrode and has its surface made flat. The source/drain regions are formed in the polysilicon layer on the surface of this flat dielectric layer. In another embodiment, a dielectric layer has a 2-layered structure with sidewall insulating layers located on sidewalls of a gate electrode and another insulating layer covering a surface of the gate electrode and surfaces of the sidewall insulating layers. By having larger film thickness of the dielectric layer in the vicinity of a side portion of the gate electrode than that above the gate electrode, the electric field concentration is modified in the vicinity thereof.

Thin film transistor and manufacturing method thereof

A groove is formed at a surface of a p.sup.- -well region. One of source/drain regions of each of access transistors has an n.sup.- -impurity region and an n.sup.+ -impurity region forming an LDD structure. Another n.sup.- -impurity region is disposed such that n.sup.+ -impurity region is located between these n.sup.- -impurity regions, and is formed at the whole bottom surface of groove. Thereby, it is possible to provide a semiconductor memory device of a high performance including an SRAM in which resistance against soft error is improved, a junction leak current is reduced and a current consumption during standby can be reduced.

Semiconductor memory device and method of manufacturing the same

A polycrystalline silicon film which is to be a channel is in a trench provided in a main surface of a silicon substrate. A gate insulating film is on the periphery of a polycrystalline silicon film. A gate electrode is on the periphery of the gate insulating film. A silicon oxide film is on the periphery of the gate electrode. A source/drain film is on the periphery of the silicon oxide film. A silicon oxide film is on the periphery of the source/drain film. A source/drain film is electrically connected to the polycrystalline silicon film. A source/drain film is electrically connected to the polycrystalline silicon film. Since the polycrystalline silicon film extends along the depth direction of trench, a channel length can be sufficient to prevent a short channel effect. Also, compared to the case in which an epitaxial layer is used as a channel, since the polycrystalline silicon film is used as a channel, the time required for manufacturing the device can be shortened.

Vertical field effect transistor with a trench structure

A structure of a thin film transistor capable of reducing the power consumption in the waiting state and stabilizing the data holding characteristic in application of the thin film transistor as a load transistor in a memory cell in a CMOS-type SRAM is provided. A gate electrode is formed of a polycrystalline silicon film on a substrate having an insulating property. A gate insulating film is formed on the gate electrode. A polycrystalline silicon film is formed on the gate electrode with the gate insulating film interposed therebetween. Source/drain regions including a region of low concentration and a region of high concentration are formed in one and another regions of the polycrystalline silicon film separated by the gate electrode. Thus, the thin film transistor is formed. The thin film transistor is applied to p-channel MOS transistors serving as load transistors in a memory cell of a CMOS-type SRAM. P-channel MOS transistors are connected to n-channel MOS transistors serving as driver transistors in the memory cell. The n-channel MOS transistors are formed in a p-type well region, and the p-channel MOS transistors are formed on an interlayer insulating film on the n-channel MOS transistors.

Growing community of inventors

Tokyo, Japan

Kazuhito Tsutsumi