Nec Corporation

Oki Electric Industry Co., Ltd.

Kazuhito Takai

Kazuhumi Takada

Satoshi Hasegawa

Katsuhito Watanabe

Shiro Fujihara

Masatsugu Suzuki

Takuro Yamamoto

Masahiro Higashi

Yukihiro Kimura

A data broadcasting system is provided which is capable of achieving display intended and desired by a provider of data broadcasting contents. The data broadcasting system includes a transmitting system and a receiver. The transmitting system includes an HD (High Definition)/SD (Standard Definition) converting section to convert HDTV (High Definition Television) data contents into data contents having a resolution applicable to an SDTV (Standard Definition Television) monitor to obtain SDTV data contents and a multiplexing section to multiplex the SDTV data contents, HDTV video contents, and HDTV data contents. The receiver has a multiplexing separation section to separate the data broadcasting contents received from the transmitting system into the SDTV data contents, the HDTV video contents, and the HDTV data contents, a down-scaling section to convert a resolution of the HDTV video contents into a resolution applicable to the SDTV monitor to obtain SDTV video contents, and a video/data synthesizing section to synthesize the SDTV video contents and the SDTV data contents to obtain display data to be used in the SDTV monitor.

Data broadcasting system, and data broadcasting contents transmitting system, receiver, and format converting method used in same

A digital video communication system includes, at a source site, an embedding circuit for embedding a digital watermark in a digital video stream to produce a watermarked digital video stream, and a multiplexer for multiplexing a text data stream with the watermarked digital video stream to produce a multiplexed signal. At a sink site, the system includes a demultiplexer for demultiplexing the multiplexed signal for recovering a watermarked digital video stream and a text data stream. A digital watermark detector is provided for detecting the digital watermark embedded in the recovered digital video stream. A synchronizer responds to the detected digital watermark for synchronizing the recovered text data stream to the recovered video stream.

Communication system using digital watermark for synchronizing multiplexed text data to video frames

A digital satellite broadcast receiving system is proposed in which the necessary packets of an MPEG2-based transport stream can be transferred to the system memory of a computer to facilitate processing of packets by a CPU. The system has means for filtering packets, by packet ID, from an MPEG2-based transport stream, which is output by a digital satellite broadcast tuner, to facilitate section formation from packets of the MPEG2-based transport stream by a CPU of a computer, filtering being performed after the transport stream is descrambled if the broadcast is a subscription broadcast; a buffer memory for storing the filtered data, which has been output by the filter means, until the data can be accessed by a host bus; and DMA control means for transferring, by direct memory access, content of the buffer memory to the system memory of the computer via the host bus.

Digital broadcast receiving system in information processor

In a system operable in response to a data stream sent to a first receiving device in one-to-one communication via a system bus, the data stream is also simultaneously delivered to a second receiving device via the system bus in parallel. The second receiving device can be implemented by the use of a simple circuit and can quickly process or display the data stream.

Data receiving device capable of executing simultaneous reception operation

A time/data adjustment device automatically synchronizes the time in a computer to the time information contained in signals from a broadcast satellite even when the computer is turned off. A broadcast station outputs video data and audio data of a broadcast program, electronic program guide (EPG) and time/date information from a satellite antennae. A geostationary satellite relays the signals to a earth station. A satellite receiving subsystem of the computer, using a stream separator, separates video data, audio data and other data, the EPG and date information are sent to the computer through a bus controller. In the computer, a device driver software acts as the interface between the subsystem and an operating system of the computer to renew the date data in the application software, and also inputs the date data in the real-time clock circuit.

Method and device for time/date adjustment for computer

To reduce access frequency to a CPU for recording/reproducing digital audio data, a control system of FIFO memories of the invention applied to an sound codec apparatus comprises means (2, 4, 7, 9 and 10) for controlling a first and a second FIFO memory (3 and 8) to store recording data sequentially and to output stored recording data sequentially when the apparatus is used exclusively for recording; and controlling the first and the second FIFO memory to store the reproducing data sequentially and to output the stored reproducing data sequentially when the apparatus is used exclusively for reproducing.

Control system of FIFO memories

In a card type recording medium containing a data area where data containing ID information of a holder are recorded, and an image area where image data are recorded, in the image area are recorded second image data which are generated by transforming first image data specifying the holder to frequency-area data, adding the transformed frequency-area data with the ID information and inversely transforming the added data to image signals.

Card recording medium, certifying method and apparatus for the recording

A multiple-plane frame buffer is effectively accessed which is provided in a video signal generator in a raster-scan type computer system. The video signal generator further includes a video controller preceded by the multiple-plane frame buffer. The video controller receives multiple-bit-per-pixel data from the multiple-plane frame buffer and applies three primary analog data to a raster-scan display. There is provided a pixel data writing controller which is arranged to store a first multiple-bit-per-pixel data defining each color of image pixels and a second multiple-bit-per-pixel data defining each color of background pixels. The pixel data writing controller selectively applies one of the first and second multiple-bit-per-pixel data to the multiple-plane frame buffer in response to a control signal applied thereto.

Arrangement and method of accessing frame buffer in raster-scan type

For use in a character display device, a modifying device comprises first and second memories. The first memory memorizes a character code representative of a character which should be displayed. The second memory memorizes an attribute or characteristic code and a selection code which cooperatively determine modification of the character. The character code, the attribute code and the selection code are read out of the first and the second memories by an address signal which is supplied from a supplying section. Responsive to the character code, a character pattern generating circuit generates a character pattern to supply the character pattern to first through N-th modifying circuits, where N represents a positive integer which is not less than two. Responsive to the attribute code, the first through the N-th modifying circuits modify the character pattern into first through N-th modification signals, respectively, to supply the first through the N-th modification signals to a selecting circuit. Responsive to the selection code, the selecting circuit selects at least one of the first through the N-th modification signals as a modified signal representative of the character with modification.

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Tokyo, Japan

Kazuhito Takai