Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Other

Kazuhito Matsukawa

Hidekazu Yamamoto

Shigeru Harada

Akio Nishida

Hiroshi Adachi

Jun Shibata

Yasuhiro Kimura

Tomonori Yamaoka

Makoto Kobayashi

Etsushi Adachi

Hirozoh Kanegae

Kimio Hagi

Tsuyoshi Koga

Hiroshi Tobimatsu

Shinroku Maejima

Hiroshi Mochizuki

Yoshiko Higashide

Masanori Obata

Hiroshi Koya

Takemi Endoh

Hiroshi Shinyashiki

Akira Ohhisa

In a semiconductor chip A wherein an element layerhaving transistors and the like is formed on the front face, and the back face is joined to an underlying member, such as a package substrate, the thickness T is made 100 &#x3bc;m or less, and thereafter, a gettering layeris formed on the back face of the semiconductor chip A. The gettering layeris formed, for example, by polishing the back face of said semiconductor chip A using a polishing machine. Thereby, the yield of devices can be improved in the step for assembling the package.

Semiconductor chip having gettering layer, and method for manufacturing the same

There are provided a method and an apparatus for evaluating a wafer configuration which can accurately evaluate a peripheral portion of a wafer as compared with the conventional SFQR or the like, which comprises: measuring a configuration of a wafer at positions with a prescribed space within a surface of the wafer; providing a first region (W ) within the wafer surface for calculating a reference line or a reference plane from the measured wafer configuration; calculating a reference line ( ) or a reference plane ( ) in the first region (W ); providing a second region (W ) to be evaluated outside the first region; extrapolating the reference line ( ) or reference plane ( ) to the second region (W ); analyzing a difference between the configuration of the second region and the reference line or reference plane within the second region; and calculating the analyzed difference as surface characteristics.

Wafer shape evaluating method and device producing method, wafer and wafer selecting method

A method of regenerating a semiconductor wafer which allows a used wafer, even if the wafer contains a crystal defect such as a COP, to be regenerated into a high-quality semiconductor wafer is provided. A used silicon wafer is polished in a step S Next, the used silicon wafer is immersed in mixed acids including at least two kinds of acids in a step S A surface treatment is performed on the used silicon wafer to planarize the surface of the used silicon wafer in a step S Then, a high temperature annealing process is performed in a step S to ultimately obtain a regenerate wafer. The high temperature annealing process includes either a first high temperature annealing process which is performed at a high temperature of 1200&deg; C. or higher in an argon atmosphere for 30 to 60 minutes, or a second high temperature annealing process which is performed at a high temperature of 1200&deg; C. or higher in a hydrogen atmosphere for 30 to 60 minutes.

Method of regenerating semiconductor wafer

A semiconductor substrate that suppresses not only auto doping but also warpage can be provided by disposing an oxide film ( ) at a position in a semiconductor substrate ( ), so as to be apart from a main surface ( ) and a reverse surface ( ). The oxide film ( ) can be so disposed that it is apart not less than 200 nm from the reverse surface ( ), and extends throughout the semiconductor substrate ( ) in a thickness of 400 to 1000 nm, by implanting oxygen ion from the reverse surface ( ), followed by annealing.

Semiconductor substrate, semiconductor device, and manufacturing method thereof

A substrate having a surface on which silicon is epitaxially grown; wherein the substrate is cut from an oxygen induced stacking fault generation area of a single crystal silicon rod grown by the Czochralski method.

Substrate for epitaxial growth

The present invention is mainly characterized by providing an even surface of an interlayer insulating film for insulating and isolating an upper interconnection and a lower interconnection from each other. A lower interconnection layer is provided on a semiconductor substrate, having a pattern of stepped portions. A silicon type insulating film is provided on the semiconductor substrate so as to cover the lower interconnection layer. A silicon ladder resin film is filled in recessed portions of the surface of the silicon type insulating film for making even the surface of the silicon type insulating film. An upper interconnection layer electrically connected to the lower interconnection layer through a via hole is provided on the silicon type insulating film. The silicon ladder resin film has the structural formula: ##STR1## where R.sub.1 is at least one of a phenyl group and a lower alkyl group, R.sub.2 is at least one of a hydrogen atom and a lower alkyl group, and n is an integer of 20 to 1000.

Semiconductor device and manufacturing method thereof

Growing community of inventors

Tokyo, Japan

Kazuhito Matsukawa