Kabushiki Kaisha Toshiba

Nippon Telegraph and Telephone Corporation

Tokyo Institute of Technology

Samsung Electronics Co., Ltd.

Kazuhito Higuchi

Susumu Obata

Kazuo Shimokawa

Mitsuo Sano

Akihiro Kojima

Yoshiaki Sugizaki

Tomohiro Iguchi

Hideo Nishiuchi

Keiichiro Matsuo

Toshiya Nakayama

Tsutomu Horikoshi

Akiya Kimura

Tomoyuki Kitani

Takaaki Akimoto

Hisashi Ito

Yosuke Akimoto

Akihiko Happoya

Takeshi Miyagi

Yusaku Asano

Takashi Koyanagawa

Satoshi Suzuki

Hiroshi Koizumi

Masayuki Uchida

Akira Tojo

Masako Fukumitsu

Takayoshi Fujii

Tomomichi Naka

Izuru Komatsu

Taizo Tomioka

Michinobu Inoue

Takayuki Tajima

Yasuhide Okada

Masayuki Saito

Hideaki Fukuzawa

Hideto Furuyama

Michiko Hara

Yoshihiro Higashi

Hideo Tamura

Miyoko Shimada

Toshiyuki Terada

Tadayuki Imai

Eiichi Hosomi

Masahiro Sasaura

Shogo Yagi

Nozomu Takahashi

Hidefumi Yasuda

Noboru Sonehara

Takashi Togasaki

Yuji Iseki

Kunio Yoshihara

Hideo Shiozawa

Yasushi Shizuki

Daisuke Hiratsuka

Yasunari Ukita

Akiyuki Tate

Akihiro Sasaki

Masayuki Kii

Kazuma Hiraguri

Eiji Takagi

Haruhiko Kojima

Eizo Fujisawa

Kyoko Kato

Takeshi Hanawa

Atsushi Murakawa

Mayumi Machino

Kyoko Honma

Masafumi Sugimoto

Kazumi Takahashi

Masato Sone

Tso-Fu Mark Chang

Kyoto Kato

According to an embodiment, a capacitor includes a conductive substrate, a conductive layer, a dielectric layer therebetween, and first and second internal electrodes. The substrate has first and second main surfaces. One partial region of the first main surface is provided with first recesses. A region of the second surface corresponding to a combination of the one partial region and another partial region is provided with second recesses. The conductive layer covers the main surfaces and side walls and bottom surfaces of the recesses. The first internal electrode is provided on the one partial region and electrically connected to the conductive layer. The second internal electrode is provided on the another partial region and electrically connected to the substrate.

Capacitor and etching method

According to one embodiment, an etching apparatus includes a first container including an opening covered by a semiconductor substrate; a second container including an opening covered by a catalyst layer; a first flow path configured to communicate with the first container; a second flow path configured to communicate with the second container; a cation exchange film interposed between the first flow path and the second flow path and allowing at least protons to pass through; and an electric field applier configured to apply an electric field to the semiconductor substrate.

Etching apparatus and etching method

According to an embodiment, an etching method includes forming a first layer on a substrate having a main surface including first and second regions adjacent to each other, the first layer including a portion covering the first region and having a plurality of openings or one or more openings defining a plurality of island-shaped portions, and the first layer further including a portion as a continuous layer covering the second region, forming a catalyst layer an a portion(s) of the main surface exposed in the openings by plating, forming a second layer to cover a portion of the catalyst layer adjacent to a boundary between the first and second regions and expose a portion of the catalyst layer spaced apart from the boundary, and etching the substrate in a presence of the catalyst layer and the second layer.

Etching method

According to an embodiment, a capacitor includes a conductive substrate, a conductive layer, and a dielectric layer. The conductive substrate has a first main surface and a second main surface and is provided with a plurality of recesses on the first main surface. The conductive substrate is further provided with a plurality of holes in one or more portions each sandwiched between two adjacent ones of the recesses such that a region on a side of the first main surface has a larger porosity than a region on a side of the second main surface. The conductive layer covers the first main surface, side walls and bottom surfaces of the recesses, and walls of the holes. The dielectric layer is interposed between the conductive substrate and the conductive layer.

Capacitor

According to one embodiment, there is provided a method for manufacturing a semiconductor device. The method includes metal electroplating on a surface of a first electrode formed on a first surface of a semiconductor substrate with a plating solution which contains aggregates of a supercritical fluid and a solution of a plating metal ion and an electrolyte. The first surface includes a recess. The surface is along with a shape of the recess. The recess has a first dimension and a second dimension, and assuming that an aspect ratio of the recess is given as a ratio of the second dimension to the first dimension, a median of a particle size distribution of the aggregates is greater than the first dimension.

Method for manufacturing semiconductor device

A structural body according to an embodiment includes a conductive substrate. A main surface of the conductive substrate includes a first region and a second region adjacent to the first region and lower in height than the first region. The first region is provided with one or more recesses having a bottom, a position of which is lower than a position of the second region. A surface region of the conductive substrate on a side of the main surface includes a porous structure at a position between the second region and the one or more recesses.

Structural body and method of manufacturing the same

According to one embodiment, a capacitor includes a conductive substrate, a conductive layer, a dielectric layer, and first and second external electrodes. The conductive substrate has a first main surface provided with recess(s), a second main surface, and an end face extending between edges of the first and second main surfaces. The conductive layer covers the first main surface and side walls and bottom surfaces of the recess(s). The dielectric layer is interposed between the conductive substrate and the conductive layer. The first external electrode includes a first electrode portion facing the end face and is electrically connected to the conductive layer. The second external electrode includes a second electrode portion facing the end face and is electrically connected to the conductive substrate.

Capacitor and capacitor module

A capacitor according to an embodiment includes a substrate having a first surface and a second surface and provided with one or more first through holes each extending from the first surface to the second surface, a first conductive layer covering the first surface, the second surface, and side walls of the one or more first through holes, a second conductive layer facing the first surface, the second surface, and the side walls of the one or more first through holes, with the first conductive layer interposed therebetween, and a dielectric layer interposed between the first conductive layer and the second conductive layer.

Capacitor having trenches on both surfaces

According to an embodiment, a structure includes a substrate including a semiconductor material, wherein the substrate is provided with one or more recesses each of which has a depth direction that is equal to a thickness direction of the substrate, and the one or more recesses include a sidewall on which a plurality of grooves each extending in the depth direction are provided.

Structure and method of producing the same

According to an embodiment, a capacitor includes a conductive substrate, a conductive layer and a dielectric layer. The conductive substrate has a first main surface and a second main surface. The first main surface includes sub-regions. Each sub-region is provided with recesses or projections each having a shape extending in one direction and arranged in a width direction thereof. One or more of the sub-regions and another one or more of the sub-regions are different from each other in a length direction of the recesses or protrusions. The conductive layer covers sidewalls and bottom surfaces of the recesses or sidewalls and top surfaces of the projections. The dielectric layer is interposed between the conductive substrate and the conductive layer.

According to an embodiment, a method of forming a porous layer includes forming a porous layer containing a noble metal on a surface made of a semiconductor by displacement plating. The plating solution used in the displacement plating contains a noble metal source, hydrogen fluoride, and an adjusting agent adjusting a pH value or zeta potential. The noble metal source produces an ion containing the noble metal in water. The plating solution has a pH value in a range of 1 to 6.

Etching method and plating solution

According to one embodiment, in a processing system and determining method, a X-ray intensity of character X-rays generated by irradiating a catalytic layer of a noble metal formed on a surface of a substrate with X-rays is detected. In the processing system and the determining method, either the detected X-ray intensity or a parameter calculated using the X-ray intensity is obtained as a determination parameter. In the processing system and the determining method, based at least on the determination parameter, whether or not the catalytic layer has been formed into a state suitable for etching the surface of the substrate is determined.

Processing system for a catalytic layer of a noble metal formed on a surface of a substrate

According to one embodiment, an etching apparatus for etching a semiconductor with an aid of a noble metal catalyst, includes a reaction vessel configured to accommodate a semiconductor substrate provided with a catalyst layer including a noble metal, and a feeder configured to feed, to the reaction vessel, an oxidizer, hydrogen fluoride, an organic additive, and carbon dioxide in a supercritical or subcritical state.

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Yokohama, Japan

Kazuhito Higuchi