Motorola Corporation

Kazuhisa Tsuchiya

Satoshi Sekine

Yoshio Enosawa

Kazuya Miyazaki

Satoshi Hatsumori

Motohiro Kitajima

Taichi Morikawa

A parallel transistor circuit 10 with non-volatile function is provided on a single semiconductor body, comprising an enhancement-type MOS transistor 1 having a drain electrode 25a connected to a drain node 25c, a gate electrode 37a connected to a gate node 37c, and a source electrode 23a connected to a source node 23c; and a floating gate-type MOS transistor 3 having a drain electrode 25b connected to the drain node, a floating gate 33, a control gate electrode 37b connected to the gate node, and a source electrode 23b connected to the source node.

Parallel transistor circuit with non-volatile function

A high density DRAM having a plurality of cells each including a storage capacitor and a single control FET formed together in a trench to substantially reduce planar area of the cell. The FET drain is formed in the upper portion of a pedestal and is accessible externally through a metal line, which reduces line resistance and capacitance. Field oxide is included to isolate capacitors and reduce leakage and breakdown.

High density DRAM

Growing community of inventors

Sendai, Japan

Kazuhisa Tsuchiya