Hitachi, Ltd.

Renesas Technology Corp.

Renasas Technology Corporation

Kazuhisa Suzuki

Toshiro Takahashi

Yusuke Nonaka

Yasunobu Yanagisawa

Akira Matsumoto

Kazuo Koide

Atsuhiro Hayashi

Tatsunori Usugi

Daisuke Hamano

Masatoshi Tsuge

An eye-opening margin measurement method for a high-speed serial data reception circuit which uses a circuit for eye-opening margin measurement involving operation of a clock data recovery circuit without fixing the clock phase. In this method, an error acceleration test can also be made on received data by giving an offset pulse signal to phase information to add a jitter component. The method uses a semiconductor integrated circuit device which includes a serializer/deserializer circuit (SerDes) for receiving serial data and a reference serializer/deserializer circuit (Ref_SerDes) for receiving an accompanying clock signal. The SerDes circuit converts received serial data into parallel data through a recovery clock whose phase is controlled using phase control signal P_CS generated by the Ref_SerDes circuit. An offset pulse signal Offset_Pulse from the pulse-forming circuit is applied to the phase control signal P_CS to make eye-opening margin measurement.

Semiconductor integrated circuit device and method for evaluating an eye-opening margin

An error rate of a bit synchronous circuit is decreased to a large extent by preventing following excessively the jitters included in input data. A phase detect circuit of a bit synchronous circuit includes a majority decision circuit. The majority decision circuit counts UP0 and DN0 signals as a phase comparison result of comparing phases by a UP0 counter and a DN0 counter for a period of time, and its count number is judged by a magnitude relation determination circuit. The magnitude relation determination circuit outputs an UP signal if the UP0 signal is majority, a DN signal if the DN0 signal is majority, and a FIX signal if the UP0 signal is equal to the DN0 signal. Accordingly, since it is possible to prevent following the jitters included in input data, etc., an error rate for bit synchronization can be reduced to a large extent.

Semiconductor integrated circuit device

A semiconductor device including a clock signal generation circuit and a plurality of circuit blocks operating in synchronization with the clock signal, in which each of the plurality of the circuit blocks conducts resetting treatment receiving the interruption signal reset_in outputted in synchronization with the clock signal in the course of frequency acquisition, whereby the timing margin is improved greatly to facilitate the design of timing for a case of conducting interruption between a plurality of circuit blocks operating at high speed simultaneously and decrease circuit scale and power consumption.

Semiconductor device

A method is provided for manufacturing an integrated circuit device having a plurality of wiring layers including a first wiring layer which is not the upper most layer among the plurality of wiring layers and a second wiring layer higher than the first wiring layer in the plurality of wiring layers. An interlayer dielectric film is provided to cover the first wiring layer. Holes are then formed in the interlayer dielectric film and a mask film is formed to cover some of the holes. Etching using the mask film is then carried out and an insulating film formed on the interlayer dielectric film is removed, including the bottoms and/or insides of the holes. The mask film is then removed and a conductive member is formed inside the holes.

Method of manufacturing a semiconductor integrated circuit device having a plurality of wiring layers and mask-pattern generation method

A capacitive element Chaving a small leakage current is formed by utilizing a gate oxide filmB thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element Chas a gate electrodeE. A part of the gate electrodeE is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the capacitive element may reliably operate even at a low power supply voltage.

Semiconductor integrated circuit device and method of manufacturing the same

A capacitive element C having a small leakage current is formed by utilizing a gate oxide film B thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element C has a gate electrode E. A part of the gate electrode E is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the capacitive element may reliably operate even at a low power supply voltage.

A capacitive element C having a small leakage current is formed by utilizing a gate oxide film B thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element C has a gate electrode E. A part of the gate electrode E is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the capacitive element may reliably operate even at a low power-supply voltage.

A capacitive element C having a small leakage current is formed by utilizing a gate oxide film 9B thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element C has a gate electrode E. A part of the gate electrode E is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the capacitive element may reliably operate even at a low power-supply voltage.

A capacitive element C having a small leakage current is formed by utilizing a gate oxide film B thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element C has a gate electrode E. A part of the gate electrode E is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the may reliably operate even at a low power-supply voltage.

Growing community of inventors

Hamura, Japan

Kazuhisa Suzuki