Yamaha Corporation

Kazuhisa Okamura

Tetsuji Ichiki

Koichi Kozuki

Hideo Suzuki

Yoshio Fujita

Fumiteru Takeda

Ichiki Tetsuji

Hiroshi Hirano

A waveform data processing apparatus has a bus that transfers data signals representative of waveform data. A plurality of transmitting nodes transmit the data signals to the bus. A plurality of receiving nodes receive the data signals from the bus. A clock generator generates a word clock signal at each sampling period. A controller is responsive to the word clock signal for conducting a session of transferring the data signals within a sampling period, such that the transmitting nodes sequentially transmit the data signals in an order predetermined by the controller so as to avoid collision of the data signals within the sampling period, and each of the receiving nodes selectively admits a necessary one of the data signals outputted from the transmitting nodes and processes the admitted data signal within the sampling period.

Waveform processing apparatus with versatile data bus

A music apparatus is constructed for processing a music tone signal in response to a clock signal at each sampling period. In the music apparatus, a clock generator generates the clock signal. A signal processor is operable in synchronization to the clock signal for time-divisionally processing a plurality of music tone signals through a plurality of channels within one sampling period. A clock controller is operative during a supply duration allocated within one sampling period for supplying the clock signal to the signal processor from the clock generator to thereby operate the signal processor, and is operative during other than the supply duration within one sampling period for stopping the supplying of the clock signal to the signal processor to thereby suspend the signal processor.

Tone signal processing apparatus with intermittent clock supply

A waveform data processing apparatus has a bus that transfers data signals representative of waveform data . A plurality of transmitting nodes transmit the data signals to the bus. A plurality of receiving nodes receive the data signals from the bus. A clock generator generates a word clock signal at each sampling period. A controller is responsive to the word clock signal for conducting a session of transferring the data signals within a sampling period, such that the transmitting nodes sequentially transmit the data signals in an order predetermined by the controller so as to avoid collision of the data signals within the sampling period, and each of the receiving nodes selectively admits a necessary one of the data signals outputted from the transmitting nodes and processes the admitted data signal within the sampling period.

The inventive packet transmitting apparatus transmits packets to receiving nodes located on a network, the packet containing at least one data block composed of at least one event sequence data and a timestamp added per a predetermined number of data blocks. In the packet transmitting apparatus, the packetizing section arranges the event sequence data into data blocks and adds thereto a timestamp so as to sequentially produce packets. The transmitting section sequentially transmits the packets. An error processing section operates when an error is detected during production of the packets for stopping transmission of a regular packet containing event sequence data and for generating and transmitting a special packet containing a message indicative of occurrence of the error. The error processing section includes a computation section that computes an input timing period of the data block based on a time of the timestamp, so that the error processing section operates when the computed input timing period deviates from a predetermined time period over an allowable range for detecting the error.

Packet handler of audio data by isochronous mode

Packet transfer apparatus transmits/receives event sequence data such as audio data and music data over a fast serial network to which a plurality of devices are connected. The input section sequentially inputs event sequence data, which is sampled at a double rate by a sampling clock signal having a half period of the input clock signal. The input section can switch between a fast sampling mode where the event sequence data is sampled at a double rate by a sampling clock signal having a half period of the input clock signal and a regular sampling mode where the event sequence data is sampled at a regular rate by another sampling clock signal having the same period as the input clock signal, and further a regular packetizing section operates under the regular sampling mode for generating a packet of the inputted event sequence data in response to only one of the leading edge and the trailing edge of the input clock signal and adds the timestamp every time the predetermined number of data blocks are packetized by the regular packetizing section.

A packet receiving apparatus has a plurality of receiving buffers to receive packets from a plurality of transmitting nodes located on a network for reproduction of event sequence data through output channels. The packet contains at least one data block composed of at least one event sequence data and a timestamp added per a predetermined number of data blocks. In the apparatus, an unpacketizing section extracts the event sequence data and the timestamp from the packet. A writing section distributes the extracted event sequence data to the plurality of the receiving buffers for writing the event sequence data into the receiving buffers. A reading section reads out the event sequence data from the receiving buffers in accordance with the extracted timestamp. The receiving buffers are separately allotted to the plurality of the transmitting nodes and are further assigned to channels of the event sequence data contained in each packet of each transmitting node. The writing section distributes the event sequence data of one packet from one transmitting node to a corresponding one of the receiving buffers according to information which is contained in the packet and which identifies the transmitting node and the channel. A patch section allocates the event sequence data read out from the receiving buffers to the output channels according to either of header information contained in the packet and setting information inputted from outside.

A mixing apparatus is constructed for mixing input voice signals with each other to produce output voice signals. In the mixing apparatus, a generator has a predetermined number of internal channels for internally generating the predetermined number of input voice signals at each sample period divided into the predetermined number of timeslots to accommodate the predetermined number of the input voice signals within each sample period. A converter converts division of the sample period so as to increase a total number of the timeslots within each sample period, and distributes the predetermined number of the input voice signals to the increased number of the timeslots so as to create an extra number of free timeslots within each sample period. An interface can receive the extra number of input voice signals provided from the extra number of external channels of an external signal source disposed separately from the generator. A selector allocates the extra number of the input voice signals to the extra number of the free timeslots so as to accommodate within each sample period the total number of the input voice signals provided concurrently from both of the generator and the interface. A processor mixies the total number of the input voice signals with one another to produce the output voice signals.

Mixing apparatus with compatible multiplexing of internal and external voice signals

A signal processing apparatus executes a plurality of microprograms stored in a microprogram memory device in a time-sharing manner, so as to perform arithmetic operations on a digital signal entered by a signal input device. A delay memory device that delays the digital signal. The delay memory device has a plurality of delay areas that are independently provided for the respective microprograms, such that each of the microprograms that is being executed uses a corresponding one of the plurality of delay areas so as to delay the digital signal, and a common area that can be accessed by all of the microprograms. As a result, data such as tables for use in common by the plurality of microprograms can be stored, and the stored data can be easily used by each microprogram, without making the system complicated or increasing the cost of the apparatus.

Signal processing apparatus

A sound effect imparting apparatus, which is employed in the electronic musical instrument in order to impart a variety of sound effects to the musical tones in a variety of manners, is mainly configured by an effect program memory, a sound-effect operation portion, a mixer and a mixing information supply portion. The effect program memory stores a plurality of effect programs, respectively corresponding to a plurality of sound effects to be imparted to musical tone data, in advance. The sound-effect operation portion performs arithmetic operations and/or logical operations on its input data in accordance with the effect programs read from the effect program memory, thus imparting desired sound effects to the musical tone data. The mixer receives the musical tone data, given from an external device, and operation data, outputted from the sound-effect operation portion, representing the musical tone data to which the sound effects have been imparted. Thus, the mixer selects some of the data inputted thereto in accordance with mixing information given from the mixing information supply portion, so that the selected data are mixed together; and consequently, mixed data are supplied to the sound-effect operation portion. On the basis of the mixed data outputted from the mixer, the musical tones to which several kinds of sound effects are imparted can be produced.

Sound effect imparting apparatus

A signal processor executes a plurality of microprograms to perform delaying processing and various arithmetic computation processings of digital signals input thereto. The signal processor has a storage area divided into a plurality of divided areas corresponding, respectively, to the microprograms. The write and read of the divided areas are controlled. When an instruction for changing at least one of the microprograms is given, the write and read of the digital signals are controlled such that at least one of the digital signals stored in at least one of the divided areas corresponds to the at least one microprogram is cleared without clearing the others of the digital signals stored in the others of the divided areas.

Signal processor having a delay ram for generating sound effects

Data of desired variable data length is stored in a memory. When desired data is to be taken out of the memory, data length of the data to be taken out is designated and necessary data is selectively taken out of the memory in accordance with the designated data length. Single data may be stored over plural addresses. In that case, MSB or LSB of data to be taken out of the data stored over the plural addresses is pointed out and desired data of a desired bit number is taken out in accordance with the pointed out position and the bit number of the data. In the memory, first data and second data may be mixedly stored. The second data consists of plural bits and is divided in plural sections, each section being separately stored in the first data. The first data and the second data are separated from the data which has been read from the memory and the respective sections of the second data are assembled together to reproduce completed second data. This storage and reproduction of data contributes to an efficient utilization of the memory.

Data storage and generation device having improved storage efficiency

In order to deal with a large amount of data and achieve a high-speed data transfer, an electronic musical instrument employs the configuration providing with plural CPUs and one main memory (RAM) so that the memory is accessed by plural CPUs. Herein, each of the CPUs provides a specific data bus, so that each of them can receive and transfer data via the specific data bus. When performing a data transfer between each CPU and memory, a line connection is selectively established between the memory and selected one of the data buses, so that each CPU can easily perform a data transfer by accessing the memory via its data bus.

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Hamamatsu, Japan

Kazuhisa Okamura