Fujitsu Corporation

Kazuhisa Ohbuchi

Kazuo Kawabata

Takaharu Nakamura

An interleaving apparatus comprises a first storing unit for storing data to be transmitted and a first control unit for controlling the first storing unit so that the data to be transmitted is outputted from the first storing unit with the data to be transmitted arranged in a matrix and at least either columns or rows of the data to be transmitted randomly rearranged, facilitating the interleaving. The result is that biased distribution of data, which leads to degradation of the transmission quality, can be prevented relatively easily in a simple structure.

Interleaving method and apparatus, de-interleaving method and apparatus, and interleaving/de-interleaving system and apparatus

Interleaving method and apparatus, de-interleaving method and apparatus, and interleaving/ de-interleaving system and apparatus

An n-bit binary value corresponding to an amount of phase shift d is assigned to an SREG, and a shift operation is performed. An n-bit vector value corresponding to a decimal value &ldquo;1&rdquo; is assigned to an LAT as an initial value. Thereafter, the input from an SW is sequentially stored. An MUL performs a square operation within a Galois field GF (2 ) for the output of the LAT. A DBL performs a double operation within the Galois field GF (2 ) for the output of the MUL. The SW selects either of the outputs of the MUL and the DBL according to the output value from the MSB side of the SREG. After the shift operation and the latch operation are performed a number of times n, the n-bit output of the LAT is output as respective phase shift coefficients b through b .

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Kawasaki, Japan

Kazuhisa Ohbuchi