Sanyo Electric Co., Ltd.

Ricoh Company, Ltd.

Tokyo Sanyo Electric Co.

Niigata Seimitsu Co., Ltd.

Kazuhisa Ishiguro

Kanji Tanaka

Tsutomu Ishikawa

Masashi Arai

Ryuichi Ogawa

Yoshiaki Takahashi

Noboru Usui

Mikio Yamagishi

Yutaka Sekiguchi

Hiroyasu Yoshida

Masanori Fujisawa

Yasunori Sato

There are provided an A/D converting circuit () for converting, into a digital signal, a broadband intermediate frequency signal which is output from a frequency converting circuit (), and a DSP () for generating and outputting control data to control gains of an antenna damping circuit () and an LNA () based on a level of the broadband digital intermediate frequency signal which is output from the A/D converting circuit (), and the broadband intermediate frequency signal which is output from the frequency converting circuit () is A/D converted and supplied to the DSP (). Consequently, it is possible to reduce a frequency of a signal input to the A/D converting circuit (). Thus, it is also possible to reduce a consumed current without requiring the use a special AD converter corresponding to a radio frequency input.

Automatic gain control circuit

An arbitrary threshold value (Ei) is established which defines a boundary as to activating an RF-AGC circuit () if the value of the field intensity (Ei) of a received signal is greater than what value while the value of the field intensity of a signal at a desired frequency being a predetermined value (Ei) in a weak field area. The established value (Ei) is used to provide a threshold value establishing/controlling part () that controls the ON/OFF of the operation of the RF-AGC circuit (). In this way, a set maker or the like of an IC including an automatic gain control part () can perform a field test or the like such that a preferable value obtained by a result of the field test or the like can be used as an AGC start level (Ei), whereby an optimum AGC control can be performed based on the preferable AGC start level (Ei).

Automatic gain control apparatus for wireless communication apparatus

A differential amplifier circuit at the input stage is configured with a twin differential type having a first differential amplifier circuit () and a second differential amplifier circuit (), respective outputs of which are received by a first and a second source-grounded amplifier (M, M). The second source-grounded amplifier (M) is connected to a current mirror circuit (M, M), which is driven by the drain current of the second source-grounded amplifier (M). With this configuration, the dynamic range for the upper half portion of an alternating signal output from an output terminal (OUT) is determined by the current supply capability of the first source-grounded amplifier (M) and the dynamic range for the lower half portion is determined by the current supply capability of the second source-grounded amplifier (M). This eliminates the need of a constant current circuit of a large current for generating a signal having lower half portion in which the waveform distortion is improved.

Differential amplifier

This invention includes a gain control sectioncapable of changing an APC loop gain according to a power output level set in a power amplifier to allow suppression of variation in power output level when the power output level is low and suppression of occurrence of ringing when the power output level is high by making the loop gain high when the power output level is low and making the loop gain low when the power output level is high.

Automatic power output control circuit

An antenna damping circuit in which the frequency characteristics of damping amount can be made substantially flat by providing a resistor (Ra) between PIN diodes (D, D) having a resistance varying upon application of a control voltage (Vc) and a capacitive dummy antenna circuit (), and setting its resistance high enough to neglect the capacity of the dummy antenna circuit () sufficiently when the dummy antenna circuit () is viewed from the side of the PIN diodes (D, D) thereby substantially eliminating the influence of capacity of the dummy antenna circuit ().

Antenna damping circuit and high frequency receiver employing same

A plurality of low-pass filters () are cascaded to the post stage of an OTA () and a plurality of high-pass notch filters () are cascaded further to the post-stage thereof so that a high-pass filter having a Q is not connected to the output of the OTA () having a high output impedance and a capacitor having a low capacitance is not connected with the output of th OTA () thus preventing multifeedback and avoiding such problems as the zero point of the notch filter (BEF) deviates from a design value or oscillation takes place.

Filter circuit

A second operational amplifier () is arranged, as an interface circuit (), between a first operational amplifier () outputting the control voltage (Vcd) of a dummy filter () and a main filter (), and the reference voltage (Vr) of the second operational amplifier () is optimized such that the control voltage (Vcd) obtained by using the dummy filter () is converted through the interface circuit () into a control voltage (Vcm) most suitable for the main filter (), thereby obtaining a control voltage (Vcm) most suitable for regulating the frequency characteristics of the main filter () to desired characteristics.

Automatic regulator of filter

By connecting an antenna damping circuit () and a bypass switch () in series and connecting the series circuit and an LNA () in parallel, it is possible to inhibit a generation of a signal path for connecting the bypass switch () to the LNA () in series in an operation of the LNA () and to prevent a noise factor of the LNA () from being deteriorated due to an on resistance of the bypass switch ().

Automatic gain control circuit and low noise amplifying circuit

A first MOS transistor (M) and a second MOS transistor (M) constitute a cascode amplifier. The second MOS transistor (M) is in a differential connection with a gain control MOS transistor (M), which has its gate supplied with an AGC control voltage (VAGC), and it is arranged that the device area ratio of the second MOS transistor (M) to the gain control MOS transistor (M) is one to N (where N&#x2267;1). In this way, even in a region where the AGC control voltage (VAGC) is small, abrupt variations of the gain can be suppressed, while the drain current of the first MOS transistor (M) can be kept constant independently of the gain control.

An idling current setting circuit () includes: current setting transistors (Q, Q) connected to output transistors (Q, Q) in a driver () in current mirror form; a plurality of current setting resistors (Rto R); and a plurality of switches (ASWto ASW) for switching to any of the current setting resistors (Rto R). This enables the idling current to be set by the current mirror ratio between the current setting transistors (Q, Q) having no connection with the open gain of the power amplifier and the output transistors (Q, Q), so that the idling current can be arbitrarily set independently of the open gain.

Power amplifier and its idling current setting circuit

A received spread spectrum signal is despread by a first despreading circuit, and according to this first despread signal, a synchronizing signal generator (PLL) generates a signal in phase with the first despread signal. According to the output signal from the synchronizing signal generator, a spreading code generator generates a plurality of Spreading codes out of phase with one another. The plurality of spreading codes are supplied to a second despreading circuit, which despreads the received spread spectrum signal by the plurality of spreading codes, and thus, a plurality of second despread signals are obtained. A correlation detector detects the correlation between the spread spectrum signal and each of the plurality of spreading codes on the basis of the plurality of second despread signals. According to the correlation results, a control circuit determines the direction in which to shift the phase of the plurality of spreading codes with respect to the received spread spectrum signal. The control circuit sequentially shifts the phases of the spreading codes until a spreading code with an optimum phase is obtained which is then supplied to the first despreading circuit and maintained. In this way, a spreading code with an optimum phase is used in the first despreading circuit, and the spread spectrum signal is despread to the original bandwidth accurately.

Spread spectrum signal receiving apparatus

In a spread spectrum signal receiver, a frequency divider circuit divides the frequency of the output signal of a VCO having a phase synchronized with that of the output signal of first multiplier. A first spreading code generating circuit generates a spreading code in response to the output signal of the frequency divider circuit. A second spreading code generating circuit generates first through third spreading codes in response to the spreading code. A selection circuit selects one of the first through third spreading codes. A second multiplier despreads the spectrum using the spreading code output from the selection circuit. A correlation detector circuit detects correlation from the output signal of the second multiplier and a control signal generates a delay or advance control signal in response to the detected correlation. The frequency dividing ratio of the frequency divider circuit is switched according to the delay or advance control signal. The timing of generating a spreading code can be regulated by changing the frequency dividing ratio, and then the timing of the spreading code of the transmitter side and that of the receiver side coincide.

Spread spectrum signal receiver

An amplifier circuit includes a negative feedback connected amplifier and a series circuit comprising a capacitor, one end of which is connected to an output terminal of the amplifier, and a resistor, one end of which is connectable to a reference potential. A comparator is provided which has first and second inputs and one output. The first input is connected to a junction between the capacitor and the resistor, the second input is connected to an output of the amplifier, and the output of the comparator is connected to one input of the amplifier. The comparator does not react to an AC signal of a specific frequency band, but operates to set the output offset voltage only to one fractional part of the transition gain, and therefore operates to accomplish offset compensation without using a large capacitor.

Amplifier circuit

A FSK data signal voltage inputted from an input terminal 4 is converted into current by a resistance R.sub.1 and then the current is differentially amplified with respect to a reference voltage of a capacitor C.sub.1 in a second differential amplifier circuit 2. As a result, a waveform-shaped signal is generated from each collector of transistors Q.sub.2 and Q.sub.3 constituting the second differential amplifier circuit 2. Meanwhile, the FSK data signal inputted from the input terminal 4, after an alternating current signal component thereof is removed, is applied to a third differential amplifier circuit 3 wherein a difference between the signal and the reference voltage of the capacitor C.sub.1 is amplified. Charging/discharging the capacitor C.sub.1 is controlled in response to an output of the third differential amplifier circuit 3.

FSK data waveform shaping circuit

An amplification circuit including a differential amplifier is disclosed. An npn transistor portion of the differential amplifier has its base provided with negative feed back, the base potential is brought to a constant potential, i.e. a virtual ground potential. The voltage between the base and emitter of the transistor is thus kept constant, and the internal resistance of the emitter does not change in accordance with the change of the emitter current. As a result, since the transistor responds only to an input signal current converted by a resistor and operates, the linearity between the input and the output of the differential amplifier is improved.

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Gunma, Japan

Kazuhisa Ishiguro