Nippondenso Co., Ltd.

Nippon Soken, Inc.

Denso Corporation

Nippon Steel Corporation

Kazuhiro Tsuruta

Seiji Fujino

Mitutaka Katada

Masami Yamaoka

Akiyoshi Asai

Tadashi Hattori

Seizi Huzino

Harutsugu Fukumoto

Mitsutaka Katada

Hiroaki Tanaka

Takeshi Enya

Hiroaki Himi

Hiroshi Ishino

Masaki Matsui

Jun Kawai

Nobuyuki Kato

Michitoshi Onoda

Megumi Suzuki

Nobuaki Kawahara

Takao Izumi

An electronic device includes an electronic component, a joining member to be mechanically joined with the electronic component, and a metal conductor located between the electronic component and the joining member to mechanically join the electronic component and the joining member. The metal conductor is made of porous noble metal to have pores, and includes an end surface without being covered by the electronic component and the joining member. Furthermore, a reinforcing resin is impregnated from the end surface of the metal conductor to the pores inside of the metal conductor, so as to mechanically reinforce the metal conductor.

Electronic device and method of manufacturing the same

In a method of manufacturing a silicon carbide semiconductor device, a semiconductor substrate made of silicon carbide and having first and second opposing surfaces is prepared. The second surface of the semiconductor substrate is processed so that a surface roughness of the second surface is less than or equal to 10 nm and a value of (100%-reflectance-transmittance) at a wavelength of a laser light is greater than or equal to 80%. A metal layer is formed on the second surface of the semiconductor substrate after the processing the second surface. The metal layer is irradiated with the laser light and thereby an ohmic electrode is formed on the second surface.

Method of manufacturing silicon carbide semiconductor device

A plurality of grooves, each having a depth of 10 &mgr;m or more and arranged adjacent to each other, are formed at a predetermined portion of a semiconductor substrate where a passive element is formed. Then, a thermal oxidation treatment is performed to let an oxide film grow from an inside surface of each groove so as to fill an inside space of the groove with a thermal oxide film thus grown and turn an entire portion intervening between adjacent grooves into a thermal oxide layer. Each groove has a width of 1 &mgr;m or less, and a width of a semiconductor material intervening between two adjacent grooves is 81.8% or more with respect to the groove width.

Semiconductor substrate for a one-chip electronic device and related manufacturing method

A semiconductor device, which can realize a high speed operation of a transistor with a small leakage current whenever such operation is required, is disclosed. A SOI layer is formed on a monocrystalline silicon substrate through a silicon oxide film, and C-MOS circuits (inverter circuits) are configured with P-channel type MOSFETs and N-channel type MOSFETs on the layer. A bias electrode for P-channel is disposed within the silicon oxide film facing the P-channel type MOSFETs, while a bias electrode for N-channel is disposed within the silicon oxide film facing the N-channel type MOSFETs. A bias voltage switching circuit applies electric potentials to the bias electrodes for the P-channel and the N-channel to increase the respective absolute values of threshold voltages of the P-channel type and N-channel type MOSFETs when the MOSFETs are in a waiting state and applies the electric potentials to the bias electrodes for the P-channel and the N-channel to reduce the respective absolute values of threshold voltages of the P-channel type and N-channel type MOSFETs when the MOSFETs are in an operating state.

Semiconductor device

A semiconductor device of SOI structure formed by the mesa isolation method, which can sufficiently reduce the wiring capacitance even if the width of the isolation trench is large. An SOI layer which constitutes an element region is formed by forming a buried oxide film in a silicon substrate, forming an isolation trench in the buried oxide film and burying an isolating material in the isolation trench. By the formation of the SOI layer with the isolating material, a dummy SOI layer is formed in a field part other than the element region. Then, by the formation of a MOSFET gate wiring on the dummy SOI layer, the wiring capacitance is reduced. Furthermore, the dummy SOI layer is completely depleted when the MOSFET threshold value is applied to the gate wiring.

Semiconductor device having an SOI structure of mesa isolation type and

A protective circuit that can maintain effectiveness when excess voltages of both polarities are applied is placed between the input terminal of an internal CMOS inverter and an input pad. The protective circuit includes a protective resistor, a P-channel MOSFET and an N-channel MOSFET. The N-channel MOSFET is placed between a connecting line and a ground terminal with the gate terminal of the MOSFET connected to the connecting line. The P-channel MOSFET is placed between the connecting line and the ground terminal with the gate terminal of the MOSFET connected to the connecting line. The P-channel MOSFET releases excess negative voltage from the outside using ON-state current and the N-channel MOSFET releases excess positive voltage from the outside using ON-state current.

Semiconductor integrated circuit device having excellent dual polarity

A pn diode as an electrostatic discharge protection element of a MOSFET in a semiconductor device having an SOI structure to enable large current to flow is disclosed. N.sup.+ layers and p.sup.+ layers are formed on a surface of an element-isolation region isolated from another element region by dielectrics, and a polycrystalline silicon layer is formed by burying under these. Accordingly, the n.sup.+ layer and p.sup.+ layer and the n.sup.+ layer and p.sup.+ layer are respectively connected electrically via the polycrystalline silicon layer, structuring pn diodes. Consequently, the respective pn diodes become vertical pn junctions and it becomes possible to allow large current flow. Additionally, a MOSFET is formed on the dielectric in another element region, and a pn diode functions as an electrostatic discharge protection element of this MOSFET.

Semiconductor device having SOI structure and method for fabricating the

A semiconductor device of an SOIMOSFET comprising a semiconductor substrate, an insulating layer and a thin film single-crystalline semiconductor layer, the insulating layer containing a floating electrically conductive layer buried therein at a portion corresponding to the channel, the floating electrically conductive layer being electrically insulated from the other portions, the semiconductor device further comprising an electrode adjacent to the floating electrically conductive layer for applying a voltage by which an electric charge is injected into and stored in the floating electroconductive layer.

SOI MOSFET with floating gate

A semiconductor circuit structure including a semiconductor substrate portion and at least one region provided on one main surface thereof insulatedly isolated from other regions provided on the same surface, by burying means made of an oxide film, the burying means including a bottom flat portion and at least one side wall portion provided at least in the vicinity of an edge portion of and integrally formed with the bottom flat portion, thereby a semiconductor circuit structure provided with a plurality of insulatedly isolated regions on a main surface thereof and having a high withstand voltage can be obtained in a short production process.

Semiconductor substrate structure for producing two isolated circuits on

In a method of bonding semiconductor substrates, a plurality of the semiconductor substrates are first prepared. Surfaces of the semiconductor substrates are mirror-polished. The mirror-polished surface of at least one of the semiconductor substrates is then provided with a hydrophilic property in such a way that an oxide layer is formed on the mirror-polished surface by exposing the mirror-polished surface to an atmosphere of at least one of an oxygen ion and an oxygen radical. A water molecule is then adhered to the mirror-polished surface. The semiconductor substrates then contact with each other through the mirror-polished surface. The contacted semiconductor substrates are then heated. According to such a method of bonding, the semiconductor substrates are strongly bonded to each other with hardly an unbonded region even if the semiconductor substrates are heated at a low temperature.

Method of bonding semiconductor substrates

A semiconductor device of vertical arrangement includes an anode region formed of a first semiconductor substrate and a second semiconductor substrate joined with the first semiconductor substrate. The first semiconductor substrate forms a high-resistance layer with a predetermined impurity density, and the second semiconductor substrate forms a low-resistance layer whose impurity density is higher than that of the high-resistance layer. A PN junction is formed inside the first semiconductor substrate. The periphery of the first semiconductor substrate including the PN junction is configured in an inverted mesa structure and coated with an insulation material. With this arrangement, the semiconductor device has a high withstand voltage and enables an employment of a large diameter wafer.

Semiconductor power device having walls of an inverted mesa shape to

A dielectric buried layer is formed inside substrates which are directly bonded together. Firstly, a groove or a recess, or both are formed on the principal bonding plane of one of at least two kinds of semiconductor substrates to be bonded together. Once the semiconductor substrates are bonded together, the groove and recess form a space, which is filled with dielectric. Before forming the dielectric buried layer, the invention carries out a process of removing potential damage from corners of the groove and/or recess.

Method of producing semiconductor substrate having dielectric separation

A semiconductor circuit structure including a semiconductor substrate portion and at least one region provided on one main surface thereof insulatedly isolated from other regions provided on the same surface, by an burying means made of an oxide film, the burying means including a bottom flat portion and at least one side wall portion provided at least in the vicinity of an edge portion of and integrally formed with the bottom flat portion, thereby a semiconductor circuit structure provided with a plurality of insulatedly isolated regions on a main surface thereof and having a high withstand voltage can be obtained in a short production process.

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Nishio, Japan

Kazuhiro Tsuruta