Seiko Instruments Inc

Ablic Inc.

Sii Semiconductor Corporation

Sti Semiconductor Corporation

Kazuhiro Tsumura

Ayako Inoue

Takeshi Morita

Jun Osanai

Kaoru Sakaguchi

Yoshitsugu Hirose

Naoto Kobayashi

Ayako Kawakami

A bipolar transistor is capable of reducing variations in electrical characteristics. A bipolar transistorincludes: a collector regionwhich is a predetermined region in a P-type semiconductor substrate; a base regionwhich is formed within the collector regionand is an N-type well region; a polysiliconformed on the base regionvia an insulating filmand having an outer periphery, as viewed in a plan view, in a rectangular ring shape; and a P-type emitter regionsurrounded by the polysiliconand formed within the base region. The polysiliconincludes an extension portionextending inside a contact regionof the base regionand electrically connected to the base region

Bipolar transistor and semiconductor device

An ESD protection circuit is connected between a Vterminal and a Vterminal and is connected in parallel with an internal circuit which operates at an operating voltage and is damaged at a damage voltage or higher to protect the internal circuit from electrostatic discharge. The ESD protection circuit includes ESD protection elements connected in series. The ESD protection elements are transistors, diode elements, or a combination thereof. A sum of current-voltage characteristics of the ESD protection elements at a voltage higher than the operating voltage is higher than the operating voltage and lower than the damage voltage, until reaching a discharge current value or higher capable of protecting the internal circuit.

ESD protection circuit and semiconductor device

A reference voltage generation device () includes a constant current circuit () configured to output a constant current; and a plurality of voltage generation circuits () each configured to generate an output voltage based on the constant current, wherein the constant current has a correlation represented by a first gradient with respect to a temperature change, and wherein a plurality of the output voltages from the plurality of voltage generation circuits () have correlations represented by second gradients that are inverse to the correlation represented by the first gradient with respect to the temperature change and have different gradient indices. The reference voltage generation device () is configured to generate a reference voltage based on the constant current and the output voltage of at least one voltage generation circuit selected from the plurality of voltage generation circuits.

Reference voltage generation device

In a semiconductor device that uses an N-channel MOS transistor as an electrostatic protection element, the N-channel MOS transistor has a plurality of electric field relaxing areas, three of which have in a longitudinal direction three different impurity concentrations decreasing from an N-type high concentration drain region downward, and three of which have in a lateral direction three different impurity concentrations decreasing from the N-type high concentration drain region toward a channel region. An electric field relaxing area that is in contact with the electric field relaxing areas in the longitudinal direction and with the electric field relaxing areas in the lateral direction has the lowest impurity concentration.

Method of manufacturing a semiconductor device

To provide a voltage regulator capable of switching a voltage of an output terminal from an internal voltage to an external voltage while suppressing an increase in circuit scale. The voltage regulator includes a voltage output circuit configured to generate a constant internal voltage lower than an external voltage applied to an input terminal from the external voltage and supplying the constant internal voltage to an output terminal, a temperature sensing circuit configured to decrease an output voltage of an output node thereof according to a rise in temperature, an overheat detection circuit connected to the output node of the temperature sensing circuit and a test terminal, and a voltage detection circuit connected to the output node of the temperature sensing circuit and the test terminal.

Voltage regulator having an overheat detection circuit and test terminal

Semiconductor device having an electrostatic protection element

Provided is a small-area one-time programmable semiconductor memory device that uses a PNPN structure, which is parasitically generated in a CMOS process. An N-type region provided in a location other than both ends or a P-type region provided in a location other than both the ends is put into a floating state so that PNPN current flows, and a thermal breakdown of a resistor caused by this current is used as a memory element.

Non-volatile semiconductor memory device

A semiconductor device includes a power element and a heat sensing element configured to detect a temperature of the power element. The power element includes lateral MOS transistors having drains and gate electrodes, two of the drains being shorter in length than the remaining drains and two of the gate electrodes being shorter in length than the remaining gate electrodes. The heat sensing element has a rectangular shape and is disposed between the two shorter drains and the two shorter gate electrodes to accurately detect the temperature of the power element.

Semiconductor device

Provided is a voltage divider circuit having a small area and good accuracy of a division ratio. Among a plurality of resistors of the voltage divider circuit, each of resistors having a large resistance value, that is, resistors (1/4R, 1/2R, 1R, 9R, 10R) having high required accuracy of ratio includes first unit resistors (A) that have a first resistance value and are connected in series or connected in parallel to each other, and each of resistors having a small resistance value, that is, resistors (1/16R, 1/8R) having low required accuracy of ratio includes second unit resistors (B) that have a second resistance value smaller than the first resistance value and are connected in parallel to each other.

Voltage divider circuit having at least two kinds of unit resistors

A semiconductor device includes a power element and a heat sensing element configured to detect a temperature of the power element. The power element includes lateral MOS transistors having drains, two of the drains being shorter in length than the remaining drains, and the heat sensing element has a rectangular shape and is disposed between the two shorter drains to accurately detect the temperature of the power element.

A power element and a temperature sensing element are formed on the same semiconductor substrate, and one end of a PN junction of the temperature sensing element is connected to a ground potential (VSS) or a power supply potential (VDD) through an intermediation of a resistor. A sum of a potential difference between both ends of the PN junction and a potential difference between both ends of the resistor is used as a temperature detection signal. The temperature sensing element can thus be formed in a recess formed in the power element while avoiding latch-up.

A non-volatile semiconductor memory device has a semiconductor substrate, an element isolation region disposed in a surface of the semiconductor substrate, a well region disposed along one principal surface of the semiconductor substrate, source and drain regions arranged in the well region, a gate oxide film arranged on the surface of the semiconductor substrate between the source region and the drain region, a floating gate disposed on the gate oxide film, and an insulating film disposed on a surface of the floating gate. A control gate is capacitively coupled to the floating gate disposed through intermediation of the insulating film. A resistive element is serially connected to the control gate. Write characteristics of the non-volatile semiconductor memory device are improved as a result of a delay effect of the resistive element serially connected to the control gate.

A non-volatile memory circuit is formed of a P-channel MOS transistor and includes a P-channel non-volatile memory element having a floating gate and a control gate capacitively coupled together. A resistor divider has a first resistor and a second resistor for dividing a voltage difference between a power supply voltage and a ground voltage. A divided voltage output of the resistor divider is connected to the control gate. First and second switches are connected in parallel to the respective first and second resistors. The first and second switches are controlled so that a voltage of the control gate is set to a voltage of the divided voltage output which maximizes an electric field between a pinch-off point and a drain point of the P-channel MOS transistor in a writing mode.

Non-volatile memory circuit

Provided is a semiconductor device including, on the same semiconductor substrate, a transistor element, a capacitor, and a resistor. The capacitor is formed on an active region, and the resistor is formed on an element isolation region, both formed of the same polysilicon film. By CMP or etch-back, the surface is ground down while planarizing the surface until a resistor has a desired thickness. Owing to a difference in height between the active region and the element isolation region, a thin resistor and a thick upper electrode of the capacitor are formed to prevent passing through of a contact.

Semiconductor device and method of manufacturing the same

Provided is a semiconductor memory circuit excellent in long-term reliability and reading characteristics and having low current consumption. The semiconductor memory circuit includes: a first inverter; a first non-volatile memory, which is electrically writable; a second inverter; and a second non-volatile memory, the first inverter having an output connected to a source of the first non-volatile memory, the first non-volatile memory having a drain connected to an input of the second inverter, the second inverter having an output connected to a source of the second non-volatile memory, the second non-volatile memory having a drain connected to an input of the first inverter, the drain of the second non-volatile memory serving as an output of the semiconductor memory circuit.

Growing community of inventors

Chiba, Japan

Kazuhiro Tsumura