Kabushiki Kaisha Toshiba

Kazuhiro Tsuji

Tetsuya Iida

Koichi Sato

Zdzislaw Czarnul

Masayuki Sahoda

Takayuki Satoh

Naoki Sugawa

A multi-input transistor circuit including a plurality of input MOS transistors having gates each serving as an analog voltage input terminal, operating in a non-saturation area and connected in parallel; and circuit for providing a constant drain/source voltage for each of the input MOS transistors, and having a current output point. A multi-input transconductance circuit including first and second MOS transistor groups having gates serving as first and second analog voltage input terminals, respectively, operating in a non-saturation area and connected in parallel; and a circuit for providing constant drain/source voltage for the transistors in each group and connected to a common source connecting point of each of the first and second MOS transistor groups, and having first and second current output terminals. The multi-input transistor and the multi-input transconductance circuit exhibit input-to-output linearity, have a wide dynamic range and are equivalent to an n-gate transistor.

Multi-input transistor circuit and multi-input transconductance circuit

A digital-to-analog conversion circuit includes a first reference voltage generation circuit for generating a plurality of first reference voltages, a plurality of second reference voltage generation circuits for generating a plurality of second reference voltages created by dividing a difference in potential between adjacent two of the first reference voltages, a first selective control circuit for, upon receiving a first digital input signal group, selecting one of the first reference voltages and applying the selected one to a specified one of a plurality of signal lines during a first period, and selecting all of second reference voltages generated in one of the plurality of second reference voltage generation circuits and applying all the selected second reference voltages to signal lines other than the specified signal line, respectively, during a second period succeeding the first period, and a second selective control circuit for, upon receiving a second digital input signal group, applying a voltage of the specified signal line to an analog output terminal during the first period, and applying voltages of the signal lines other than the specified signal line to the analog output terminal during the second period.

Digital-to-analog conversion circuit and analog-to-digital conversion

In an operational amplifier circuit, noise is lowered by using junction FETs as an input transistor pair, and an input operating point and an output operating point can be set at different potentials by connecting a capacitor between an output terminal and an inverting input terminal. For this reason, the operational amplifier circuit can be properly biased and can be operated at a low power supply voltage. In addition, since transistors other than transistors used as constant current sources are constituted by bipolar transistors, the operational amplifier circuit can have wideband frequency characteristics.

Operational amplifier with junction field effect transistors as input

A comparator device comprising a offset-compensating comparator and a positive-feedback comparator. A reference voltage and an input voltage are applied to the input terminals of the offset-compensating comparator. The non-inverting and inverting output terminals of the offset-compensating comparator are connected to the inverting and non-inverting input terminals of the positive-feedback comparator, respectively. The positive-feedback comparator starts comparing the input voltage with the reference voltage before the offset-compensating comparator finishes comparing the input voltage with the reference voltage. Hence, the comparator device operates at high speed and has a great gain. In addition, the offset voltage can be reduced. A transistor is connected between the differential input terminals of the positive-feedback comparator, for setting both differential input terminals at the same potential at the time the comparator starts comparing the input voltage with the reference voltage. Therefore, the differential inputs to the positive-feedback comparator have no noise.

Comparator device for comparing analog voltages

A plurality of segment groups constituting a D/A converter, and decoders for decoding digital signals and selecting segments constituting the segment groups are arranged on a semiconductor chip. The segments constituting the plurality of segment groups are mingled and two-dimensionally arranged. The positions of the centers of gravity of the respective segment groups are substantially matched with the center of the arranged segments.

D/A converter having centered switching sequence and centered

An A/D converter of this invention includes a first A/D converter for A/D-converting the input signal and determining upper bits of the n-bit binary code, first and second sample-hold circuits, which are alternately switched each time the first A/D converter samples the analog input signal, for sampling and holding the analog input signal, in synchronism with a sampling timing of the first A/D converter, and a second A/D converter. The second A/D converter is constituted by a reference voltage generator for generating reference voltages, based on contents of the binary code obtained by the first A/D converter, a voltage comparator for comparing the reference voltage with a voltage value of the analog input signal held in one of the first and second sample-hold circuits, which sample and hold the analog input signal corresponding to the binary code, and an encoder for encoding a comparison result output from the voltage comparator and determining lower bits of the n bits.

Growing community of inventors

Yokohama, Japan

Kazuhiro Tsuji