Elpida Memory, Inc.

Nec Corporation

Kazuhiro Teramoto

Yoji Idei

Hiroki Fujisawa

Takenori Sato

Susumu Takahashi

To provide a semiconductor device including a pair of antifuse elements at either a high level or a low level, an OR circuit that outputs different logic information for a case that at least one of the antifuse elements is at a high level and a case that both of the antifuse elements are at a low level, and an exclusive OR circuit that outputs different logic information for a case that the logic states are different from each other and a case that they are same as each other.

Semiconductor device having nonvolatile memory element and manufacturing method thereof

A semiconductor device includes a plurality of first output terminals-and a plurality of first output circuitsprovided corresponding to each of the plurality of first output terminals and coupled to a corresponding first output terminal. The semiconductor device further includes a second output circuitcoupled to a second output terminal DQS. The second output circuit automatically adjusts a slew rate based on the state transitions of the plurality of first output circuits. The second output circuit adjusts the slew rate from a first state to a second state based on a transition from first data outputted from the first output circuit to second data following said first data. The second output circuit outputs data in synchronization with the second data with a slew rate in said second state.

Semiconductor device

Auto-refresh of a semiconductor device may be controlled by setting the number of auto-refresh to be performed in a period of time, based on temperature, when an auto-refresh command is detected.

Semiconductor memory device and method of controlling auto-refresh

A semiconductor storage device is provided which enables use of an overdrive method at low voltage and for a small device area. The semiconductor device includes: memory cells; sense amplifiers, each having P-channel and N-channel MOS transistors and amplifying a signal read from a memory cell; a first power supply line connected to a source terminal of the P-channel MOS transistor provided in each of the sense amplifiers; a second power supply line which supplies an overdrive voltage to the sense amplifiers at a potential higher than a write potential of the memory cell; a third power supply line connected to an external power supply, a connection element which connects and disconnects the first power supply line and the second power supply line; a capacitance element connected to the second power supply line; and a resistance element inserted between the second power supply line and the third power supply line.

Semiconductor storage device

A semiconductor device operates in an active mode or a standby mode, and includes a substrate-potential power source line supplying a substrate potential which is higher in a standby mode than in an active mode, and a source-potential power source line supplying a source potential which is lower in a standby mode than in an active mode. During a mode shift from the standby mode to the active mode, a potential equalizing transistor is turned ON to pass a current flowing from the substrate-potential power source line to the source-potential power source line, to reduce the time length needed for shifting from the standby mode to the active mode.

Semiconductor device operating in an active mode and a standby mode

A semiconductor memory device includes a shared transistor controlling coupling between a bit line pair in a memory cell array and a bit line pair in a sense amplifier. After a word line is activated and the sense amplifier amplifies the potential difference between the bit lines of the bit line pair in the sense amplifier, the shared transistor is tuned OFF and precharge/equalizing circuit is activated to precharge the bit lines in the sense amplifier to a potential which is half the internal power source potential.

Semiconductor memory device including a sense amplifier having a reduced operating current

A semiconductor memory device is provided that is capable of detecting a short circuit defect to be detected in a memory array without causing an error due to off-current of a sense amplifier circuit. Sense amplifier circuits amplify a potential between a pair of bit lines, which occurs based on potential of memory cells selected by driving word lines and bit lines. Selection transistors are provided between the bit lines and the sense amplifier circuits. A word-SE interval control circuit included in an X timing generating circuit turns off the selection transistors and disconnects the bit lines from the sense amplifier circuits based on a signal representing a test state for expanded time when a test to expand an interval between word line driving and activation of the sense amplifier circuits and detect defect sites of the bit lines is performed.

Semiconductor memory device

A plurality of the P-channel transistors of Group A and a plurality of P-channel transistors of Group B are connected between the power-supply-voltage VCC and the ground, and an output signal SUBUP is obtained from the node C via two inverters. Each terminal of. Transistors of Group B is connected to the ground via N-channel first, second and third transistors. The first signals &phgr;1 and &phgr;2 are inputted to the gates of the first and second transistors and the output of the NOR logical circuit is inputted to the gate of the third transistor. Current performance of the P-channel transistors of Group B is adjusted to control the substrate voltage and to make the substrate voltage both higher and lower than that of normal operation by the use of the test modes. So, the substrate voltage can be changed during hold tests in a selection process to accelerate the tests and shorten the selection time.

Growing community of inventors

Tokyo, Japan

Kazuhiro Teramoto