Panasonic Intellectual Property Management Co., Ltd.

Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Kazuhiro Shimomura

Makoto Yamamoto

Ryouta Akeyama

A multiplexer for voltage measurement includes: a first switch disposed on a first channel extending between at least one high-voltage input terminal and an output terminal; a plurality of second switches respectively disposed on second channels each extending between each of input terminals other than the high-voltage input terminal and the output terminal; and a third switch disposed between a group of the plurality of second switches and an output terminal side end of the first switch. Each of the first switch and the third switch is configured to operate even by a voltage higher than a power supply voltage.

Multiplexer for voltage measurement and voltage measuring unit including the same

A signal processor includes: a plurality of first capacitors provided for respective output terminals of a plurality of multiplexers, the first capacitors having their one ends connected to the respective output terminals of the multiplexers, the first capacitors being charged in accordance with voltages outputted from the respective output terminals; a differential amplifier including an input terminal connected to the other ends of the first capacitors; a second capacitor connected between the input terminal and an output terminal of the differential amplifier; and a second switch connected parallel to the second capacitor. First switches included in at least one of the plurality of multiplexers are configured as high-voltage switches that allow operation at a voltage higher than an operating voltage of first switches included in the other multiplexer or multiplexers.

Voltage measuring device

An NchMOS transistor () is provided for muting of an output terminal () to which positive and negative output signals are outputted, and a mute switch circuit () is provided for controlling on/off of the transistor () by switching a voltage applied to the gate of the transistor (). When muting is turned off, the back gate of the transistor () is biased by resistance division between resistors (Rand R) connected in series between the output terminal () and a predetermined negative potential (VSS).

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Osaka, Japan

Kazuhiro Shimomura