Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Corporation

Yokogawa Electric Corporation

Mitsubishi Denki Kabuhsiki Kaisha

Kazuhiro Shimizu

Hajime Akiyama

Tomohide Terashima

Naoki Yasuda

Kazunari Hatade

Manabu Yoshino

Yuji Kawasaki

Toshihiro Imasaka

Junichi Yamashita

Akira Toyama

Ze Chen

Takuichiro Shitomi

Satoshi Rittaku

Masakazu Hori

Sadao Mori

Tomonori Komachi

Kazuhide Yasuda

Mariko Yao

Provided is a semiconductor device including: an N-type diffusion layer being a second region, formed in a surface portion of a P-type diffusion layer being a first region, to function as a RESURF region; an N-type buried diffusion layer being a third region formed in a bottom portion of the second region, close to a high-side circuit; and a MOSFET using the second region as a drift layer. The MOSFET includes a thermal oxide film formed between an N-type diffusion layer being a fourth region serving as a drain region and an N-type diffusion layer being a sixth region serving as a source region, and an N-type diffusion layer being a seventh region formed below the thermal oxide film. The seventh region has an end portion close to a low-side circuit, being closer to the low-side circuit than an end portion of the third region close to the low-side circuit.

Semiconductor device comprising a MOSFET having a RESURF region and higher peak impurity concentration diffusion region in the RESURF region

A high withstand voltage isolation region has a first diffusion layer of a second conductivity type formed on a principal surface of a semiconductor substrate. The high withstand voltage MOS has a second diffusion layer of the second conductivity type formed on the principal surface of the semiconductor substrate. A low side circuit region has a third diffusion layer of a first conductivity type formed on the principal surface of the semiconductor substrate. A fourth diffusion layer of the first conductivity type having a higher impurity concentration than the semiconductor substrate is formed on the principal surface of the semiconductor substrate exposed between the first diffusion layer and the second diffusion layer. The fourth diffusion layer extends from the high side circuit region to the low side circuit region and does not contact the third diffusion layer.

Semiconductor device comprising resurf isolation structure surrounding an outer periphery of a high side circuit region and isolating the high side circuit region from a low side circuit region

The semiconductor device that supplies a charging current to a bootstrap capacitor includes a semiconductor layer, an N-type diffusion region, an N-type diffusion region, a P-type diffusion region, a P-type diffusion region, an N-type diffusion region, a source electrode, a drain electrode, a back gate electrode, and a gate electrode. The N-type diffusion region and the N-type diffusion region are electrically connected to a first electrode of the bootstrap capacitor. The N-type diffusion region is supplied with a power supply voltage. The source electrode is connected to the N-type diffusion region and is supplied with the power supply voltage. The back gate electrode is connected to a region separated from the N-type diffusion region and is grounded. The breakdown voltage between the source electrode and the back gate electrode is greater than the power supply voltage.

Semiconductor device

A semiconductor device includes a well region, a buffer region, an insulating film, an electrode, and an electric field relaxing structure. An impurity concentration in the buffer region is reduced in a direction away from the active region. An end portion of the electrode is located at a position closer to the active region than an end portion of the buffer region. The electric field relaxing structure includes a plurality of RESURF layers each surrounding the buffer region in a plan view and formed in a surface layer of the semiconductor substrate.

Semiconductor device and method of manufacturing semiconductor device

A measurement device according to one aspect of the present invention includes a first controller configured to output a control signal and a second controller configured to perform a first control and then to perform a second control based on the control signal output from the first controller. The control signal designates both an input signal and a calibration signal to be converted into a digital input signal and a digital calibration signal, respectively. The input signal is input from an outside of the measurement device. The calibration signal is previously prepared. The first control is for selecting the input signal and converting the selected input signal into the digital input signal. The second control is for selecting the calibration signal and converting the selected calibration signal into the digital calibration signal and for calculating a measured value using the digital input signal converted by the first control and another digital calibration signal converted by a control performed before the first control.

Measurement device

An analog front-end circuit for measurement used as an interface between a sensor and a control device includes: an isolated part including at least an AD conversion circuit configured to serve as an interface to the sensor; a non-isolated part including at least a control circuit configured to serve as an interface to the control device; and an isolated communication unit configured to perform isolated half-duplex communication between the isolated part and the non-isolated part. The control circuit is configured to transmit an AD conversion instruction to the AD conversion circuit after providing setting for measurement to the isolated part via the isolated communication unit, obtain a result of AD conversion by the AD conversion circuit from the isolated part via the isolated communication unit, and transfer the obtained AD conversion result to the control device.

Analog front-end circuit for measurement

A first isolation trench insulates and separates a low-voltage region, a high-voltage region, and a connection region of the semiconductor layer from each other. A low-potential signal processing circuit is in the low-voltage region, and operates at a lower potential. A high-potential signal processing circuit is in the high-voltage region, and operates at a higher potential. A capacitor is on the connection region and transmits the second alternating current signal from the low-potential signal processing circuit to the high-potential signal processing circuit. The capacitor includes a low-potential electrode connected to the low-potential signal processing circuit, and a high-potential electrode connected to the high-potential signal processing circuit. First wiring layers of the low-potential electrode and second wiring layers of the high-potential electrode are capacitively coupled. Side wall surfaces of the first wiring layers and those of the second wiring layers are opposed to each other.

An SOI wafer according to the present invention includes a support substrate and an insulating layer formed on the support substrate, a predetermined cavity pattern being formed on one of main surfaces of the support substrate on which the insulating layer is provided, further includes an active semiconductor layer formed on the insulating layer with the cavity pattern being closed, the active semiconductor layer not being formed in an outer peripheral portion of the support substrate, and further includes a plurality of superposition mark patterns formed in the outer peripheral portion on the one of the main surfaces of the support substrate for specifying a position of the cavity pattern.

SOI wafer and method of manufacturing the same

A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.

Semiconductor device manufacturing method

A power semiconductor device comprises: a high-voltage side switching element and a low-voltage side switching element which are totem-pole-connected in that order from a high-voltage side between a high-voltage side potential and a low-voltage side potential; a high-voltage side drive circuit that drives the high-voltage side switching element; a low-voltage side drive circuit that drives the low-voltage side switching element; a capacitor which has a first end connected to a connection point between the high-voltage side switching element and the low-voltage side switching element and a second end connected to a power supply terminal of the high-voltage side drive circuit and supplies a drive voltage to the high-voltage side drive circuit; and a diode which has an anode connected to a power supply and a cathode connected to the second end of the capacitor and supplies a current from the power supply to the second end of the capacitor, wherein the diode includes a P-type semiconductor substrate, an N-type cathode region on a surface of the P-type semiconductor substrate, a P-type anode region in the N-type cathode region, a P-type contact region and an N-type contact region in the P-type anode region, a cathode electrode connected to the N-type cathode region, and an anode electrode connected to the P-type contact region and the N-type contact region.

Power semiconductor device

A semiconductor device includes a low-side circuit, high-side circuit, a virtual ground potential pad, a common ground potential pad and a diode, formed on a semiconductor substrate. The low-side circuit drives a low-side power transistor. The high-side circuit is provided at a high potential region, and drives a high-side power transistor. The virtual ground potential pad is arranged at the high potential region, and coupled to a connection node of both power transistors to supply a virtual ground potential to the high-side circuit. The common ground potential pad supplies a common ground potential to the low-side circuit and high-side circuit. The diode has its cathode connected to the virtual ground potential pad and its anode connected to the common ground potential pad.

Semiconductor device driving bridge-connected power transistor

An RESURF region is formed so as to surround a high-potential logic region with an isolation region interposed therebetween, in which a sense resistance and a first logic circuit which are applied with a high potential are formed in high-potential logic region. On the outside of RESURF region, a second logic circuit region is formed, which is applied with the driving voltage level required for driving a second logic circuit with respect to the ground potential. In RESURF region, a drain electrode of a field-effect transistor is formed along the inner periphery, and a source electrode is formed along the outer periphery. Furthermore, a polysilicon resistance connected to sense resistance is formed in the shape of a spiral from the inner peripheral side toward the outer peripheral side.

A semiconductor device including a high voltage element and a low voltage element, including: a semiconductor substrate having high voltage element region where the high voltage element is formed, and a low voltage element region where the low voltage element is formed; a first LOCOS isolation structure disposed in the high voltage element region; and a second LOCOS isolation structure disposed in the low voltage element region, wherein the first LOCOS isolation structure includes a LOCOS oxide film formed on a surface of the semiconductor substrate and a CVD oxide film formed on the LOCOS oxide film, and the second LOCOS isolation structure includes a LOCOS oxide film.

Growing community of inventors

Tokyo, Japan

Kazuhiro Shimizu