Kabushiki Kaisha Toshiba

Kazuhiro Shimizu

Seiichi Aritome

Kenichi Imamiya

Takashi Mori

Ken Takeuchi

Hideko Oodaira

Yuji Takeuchi

Toshitake Yaegashi

Kazuhito Narita

Hiroshi Watanabe

Riichiro Shirota

Akira Goda

Hirohisa Iizuka

Hiroaki Hazama

Fumitaka Arai

Toshiharu Watanabe

Wakako Moriyama

Norihisa Arai

Naoki Koido

Eiji Kamiya

Shinji Satoh

Tohru Maruyama

Tadashi Iguchi

Hiroaki Tsunoda

Shoko Kikuchi

Takafumi Ikeda

Kunihiro Terasaka

Kauhito Narita

In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a first polysilicon layer. A material such as salicide or a metal, which differs from second polysilicon (which forms a control gate layer), may be provided on the first polysilicon layer. With the above features, a non-volatile semiconductor memory device can be manufactured by reduced steps and be operated at high speed in a reliable manner.

Non-volatile semiconductor memory device and its manufacturing method

A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.

Semiconductor memory device capable of realizing a chip with high operation reliability and high yield

A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.

Nonvolatile semiconductor memory

According to one embodiment, a semiconductor device includes a stacked structure that is formed by laminating a first insulating film, first conductive layer, second insulating film and second conductive layer on a semiconductor substrate and in which the first and second conductive layers are connected with a via electrically, an interlayer insulating film formed to electrically separate the second conductive layer into a first region including a connecting portion with the first conductive layer and a second region that does not include the connecting portion, a first contact plug formed on the first region and a second contact plug formed on the second region. An isolation insulating film is buried in portions of the substrate, first insulating film and first conductive layer in one peripheral portion on the second region side of the stacked structure and the second contact plug is formed above the isolation insulating film.

Semiconductor device

A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.

A nonvolatile semiconductor memory device includes an element isolation insulating film buried in first trenches, a floating gate electrode formed on an element forming region with a first gate insulating film being interposed between them, and a second gate insulating film formed on upper portions of the floating gate electrode and an element isolation insulating film. The floating gate electrode is formed so as to have a side that extends from a bottom thereof to its upper portion and is substantially an extension of a sidewall of each first trench. The element isolation insulating film includes a portion located between its sidewall and the sidewall of a second trench, and the portion of the element isolation insulating film having a film thickness in a direction along the upper surface of the semiconductor substrate. The film thickness is equal to a film thickness of the second gate insulating film.

Nonvolatile semiconductor memory device

First and second semiconductor regions are formed apart from each other on a semiconductor body. A stacked gate is formed on the semiconductor body between the first and second semiconductor regions. The stacked gate has a first side surface, a second side surface opposed to the first side surface, and an upper surface. A contact material is buried in an interlayer insulating film above the semiconductor body, to be adjacent to the first side surface of the stacked gate. The contact material contacts the first semiconductor region. A first insulating film is formed on the second side surface and the upper surface, except the first side surface of the stacked gate adjacent to the contact material. A second insulating film is formed on the first side surface of the stacked gate adjacent to the contact material, and the first insulating film.

Non-volatile semiconductor memory device having memory cell array suitable for high density and high integration

A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell portion, a step of introducing impurity into the peripheral circuit portion and memory cell portion, a step of forming a first insulating film above at least the memory cell portion, and a step of annealing the semiconductor substrate into which the impurity has been introduced. The first gate electrode has a first gate length. The second gate electrode has a second gate length shorter than the first gate length.

Nonvolatile semiconductor memory device and method for manufacturing the same

Growing community of inventors

Yokohama, Japan

Kazuhiro Shimizu