Kabushiki Kaisha Toshiba

Microcomputer Engineering Ltd.

Kazuhiro Sawada

Takayasu Sakurai

Kazutaka Nogami

Mitsuo Isobe

Tetsuya Iizuka

Takayuki Ohtani

Tsukasa Shirotori

Hisashi Ueno

Akira Aono

A semiconductor device comprises a logic circuit and a memory including a timing signal generator circuit, both formed in a substrate, and a wiring connecting the logic circuit to the memory, in which a diffusion layers connected to receive a predetermined potential is located under an area of the wiring situated between the logic circuit and the memory whereby it is possible to alleviate an effect from minority carriers and a substrate potential variation.

Semiconductor device

A dynamic read/write memory in which refreshing is performed within a read/write cycle so that write recovery time is not prolonged. A word line corresponding to a current address is continuously rendered operative within a write period. When a write operation is completed, the word line is rendered operative so that refreshing is initiated. A word line is rendered operative only within a given period of a read period.

Dynamic read/write memory with improved refreshing operation

A virtual type static semiconductor memory device according to the present invention comprises a refresh detector circuit for detecting the enabling operation of a refresh control circuit and a terminal for outputting to an outside a detection signal which is generated from the refresh detector circuit. The virtual type static semiconductor memory device informs a present refresh operation to the outside when it is accessed from the outside during the time period in which a refresh operation is conducted in the semiconductor memory device. A system employing the semiconductor memory device allows a slow access at that time only and allows access to be gained to the semiconductor memory device at high speed at other times.

Virtual type static semiconductor memory device including refresh

A semiconductor memory control circuit separates an externally input operation activation signal from an operation activation signal which is transferred inside a memory, and activates the internal operation activation signal only for a predetermined period of time. This predetermined period is determined in accordance with the cycle time required to achieve refreshment of a memory cell after the external operation activation signal is activated. Thereafter, even if the external operation activation signal is in an activated state, the internal operation activation signal is inactivated. When the internal operation activation signal is in the activated state and the external operation activation signal is inactivated, the internal operation activation signal is inactivated, in accordance with activation of the external operation activation signal.

Semiconductor memory control circuit

This invention provides an intermediate potential generating circuit comprising a load element of which one end is connected to a first potential supply source, a first transistor of a first conductivity type of which one end and the gate thereof are connected to the other end of the load element, a second transistor of a second conductivity type of which one end is connected to the other end of the first transistor, and the gate and the other end thereof are connected together, a constant-voltage means connected between the other end of the second transistor and a second potential supply source for causing a specific voltage drop between the ends of the contant-voltage means, a third transistor of the first conductivity type of which one end is connected to the first potential supply source, the gate is connected to a node between the load element and the first transistor, and the other end thereof is connected to an output terminal, and a fourth transistor of the second conductivity type which is connected between the output terminal and the second supply source and of which the gate is connected to a node between the second transistor and the constant-voltage means.

Intermediate potential generating circuit

This invention provides a refresh operation control circuit for a semiconductor memory device. Two flip-flop circuits respectively temporarily hold a normal read start command signal and a refresh start command signal generated within the memory device. A normal operation/refresh operation priority determining circuit wherein 2-input logic circuits are cross-connected so that one output in each case of each of these two flip-flop circuits provides one input of the other flip-flop circuit. The priority determining circuit determines the priority of normal read operation and refresh operation in accordance with the logic level relationship of the one inputs. Either control of the start of normal read operation or control of the start of refresh operation is carried out in accordance with the output of this determination.

Refresh operation control circuit for semiconductor device

In the semiconductor memory device according to the present invention, when there is a defective portion in the memory cells, those memory cells are replaced by redundant memory cells. When defective portions are discovered in the memory cells, the fuse elements corresponding to the memory cells having the defective portions are cut off. Voltages of the select lines connected to the memory cells having the defective portions are held at an L level by the resistors. Due to this, the memory cells having the defective portions are not selected.

Growing community of inventors

Yokohama, Japan

Kazuhiro Sawada