Mitsubishi Electric Engineering Company, Limited

Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Kazuhiro Sakemi

Mikio Sakurai

Yutaka Ikeda

Shigeru Mori

Takeshi Kajimoto

Shigeru Kikuda

Yoshinori Inoue

Satoshi Kawasaki

Kenji Tokami

Tooru Ichimura

A write buffer drives in a normal operation a level in potential of an I/O line pair in accordance with data externally input to be written, whereas a burn in write buffer is controlled in a test operation by a control circuit to drive the I/O line pair in level. A column address decoder in the test operation is controlled by the control circuit to select simultaneously a plurality of bit line pairs capable of coupling with a single I/O line pair.

Semiconductor memory device capable of applying stress voltage to bit line pair

A dummy pattern that is inserted to stabilize the form of a transistor active region is implanted with an impurity of the same conductivity type as a well, and the impurity-doped region of the dummy pattern is supplied with a potential through a metal interconnection. Hence, fluctuation of a well potential due to noise hardly occurs, and a semiconductor device enduring latch up, for example, to a greater extent can be provided.

Semiconductor device with improved noise resistivity

A semiconductor memory device includes a memory cell array (1) having a plurality of memory cells arranged in rows and columns, a plurality of column select lines (3) extending over the memory cell array and coupled to received column select signals generated by a column decoder (100), a plurality of power supply lines (4) provided in parallel with the column select lines to transfer a power supply voltage from a main power supply line (130), and a plurality of ground lines (5) provided in parallel with the column select lines to transfer a ground voltage from a main ground line. A plurality of fuse elements (6) are provided for each of the column select lines. When a short-circuit is found between a column select line and power supply line or a ground line, a fuse element corresponding to the short-circuited column select line is blown off and the short-circuited column select line is isolated from the column decoder. By repairing the short-circuited column select line with a redundant column select line (60), the memory device operates correctly without an adverse effect of the short-circuit.

Semiconductor device having an improved immunity to a short-circuit at a

A semiconductor memory device includes a pull up circuit (811) for pulling up a potential of a first node (812), a pull down circuit (813) for pulling down the potential of the first node, an inverter circuit (814b) having its input connected to a first input node (814a) connected to the first node (812) and its output connected to a first output node (814c) and operating with a boosted potential Vpp, and a p channel MOS transistor (814d) connected between a boosted potential node (50c) and the first input node (814a), with its gate electrode connected to the first output node (814c). The memory device provides a signal having a higher level than the supply potential with smaller area of layout.

Semiconductor device including signal generating circuit with level

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Hyogo, Japan

Kazuhiro Sakemi