Mitsubishi Denki Kabushiki Kaisha

Renesas Electronics Corporation

Tokyo Metropolitan Industrial Technology Research Institute

Kazuhiro Sakashita

Takeshi Hashizume

Ichiro Tomioka

Satoru Kishida

Toshiaki Hanibuchi

Tatsunori Komoike

Takahiko Arakawa

Isao Takimoto

Terukazu Yusa

Yoshiki Tsujihashi

Ryo Yonezu

Masahiro Ueda

Yusuke Kobayashi

Yasushi Onishi

Shuichi Kato

Yusuke Morita

Mamoru Sakugawa

Yoshihiro Okuno

Takashi Ohya

Kazuhiro Shimakawa

Toshiki Masuda

A rocker bogie includes a first base which including a first wheel, a second wheel, and a third wheel each of which is configured to be in contact with a first flat surface, a second base including a fourth wheel which is configured to be in contact with the first flat surface, and a rotary shaft connecting the first base and the second base to each other such that the second base is rotatable with respect to the first base. The rotary shaft is parallel to a first straight line which connects a rotation center of the first wheel and a rotation center of the second wheel to each other and is disposed between a rotation center of the third wheel and the first straight line, and the fourth wheel is disposed at an opposite position to the third wheel across the first straight line.

Rocker bogie

A tuner receives broadcast data on specified channels. A channel search unit controls the tuner to search for available channels, and creates a channel map representing the available channels and a selection order thereof. A channel order setting unit changes setting about enabling/disabling of the selection and/or the selection order of the channels in the channel map. An operation input unit accepts a channel selecting operation of a user. When the user performs an operation for channel forward selection or channel reverse selection through the operation input unit, a channel switching unit changes the selection of the channel according to the channel map and causes the tuner to receive the broadcast data on the selected channel.

Broadcast receiving device and program selecting method

An object is to compatibly improve processing speed and storage capacity of semiconductor memory that the operation portion can use. Each of units (10a, 10b) each having an operation portion (11) and a memory portion (12) is formed of a single semiconductor chip. A data signal is separately stored in the two memory portions (12) in a bit-sliced form and each of the two operation portions (11) can use the 32-bit-wide data signal stored in the entirety of the two memory portions (12) through interconnections (22, 23). That is to say, each operation portion (11) can use a storage capacity twice larger than the capacity that can be ensured in a single semiconductor chip. Provided as interconnections for coupling the semiconductor chips are only the interconnections (22, 23) for transferring data signals from the two memory portions to the two operation portions (11). Hence, the bit width of the interconnections (22, 23) can be increased to increase the transmission speed of the data signals and to increase the processing speed of the device.

Bit-slice processing unit having M CPU's reading an N-bit width data

An integrated circuit device is structured by a plurality of functional modules (2a, 2b) each performing a predetermined function, each functional module including a test circuit (3) for testing the corresponding module. Each test circuit comprises a scan path (3a-3d) for receiving test data from a single common input line to perform a test and outputting a test output, a tri-state buffer (4a) for controlling an output of the test output from the scan path to a single common output line, and a scan path selecting circuit (5a) for selectively driving the tri-state buffer. All the selecting circuits in the integrated circuit device are connected in series to constitute as a whole a shift register. A selecting signal of the serial data is inputted to the shift register, so that the test output of each scan path is selectively supplied to the common output line.

Integrated circuit device comprising a plurality of functional modules

Power consumption is reduced in a semiconductor integrated circuit. In a conventional flip-flop circuit, there is a transistor between one side current electrode of a PMOS transistor (PTr7) and an node (V0) of a power source. This transistor is deleted and one side current electrode of (PTr7) is connected to an node (D2). In a similar manner, one side current electrode of (PTr13) is connected to an node (D13), one side current electrode of an NMOS transistor (NTr6) is connected to an node (D6), and one side current electrode of (NTr14) is connected to an node (D12). Thus, by deleting transistors, the capacity of transistors which are to be driven by a clock signal is reduced, and therefore, power consumption is reduced.

Semiconductor integrated circuit

It is an object to obtain a semiconductor integrated circuit with reduced power consumption without reducing operation speed. In clock input control means (27), an exclusive OR gate (26a) receives comparison data (S1 and S2) and an NAND gate (27a) receives output of the exclusive OR gate (26a) and a reference clock (T) and outputs its output, a control signal (SC1) to an AND gate (G1) and an AND gate (G2) in a data holding portion (31a). An exclusive OR gate (26b) receives comparison data (S3 and S4) and an NAND gate (27b) receives the output of the exclusive OR gate (26b) and the reference clock (T), and outputs its output, a control signal (SC2) to an OR gate (G5) and an OR gate (G6) in a data holding portion (31b). Appropriately selecting the comparison data (S1-S4) allows data transfer at high speed of input data (D), output data (Q), inverted output data (QC), and so forth.

Master-slave bistable latch with clock input control

Programmable logical blocks (3a to 3c) selected from a block library including information of a plurality of types of programmable logical blocks are disposed in a core region of a semiconductor integrated circuit (100). The degree of freedom of designing a field programmable gate array (FPGA) and the degree of integration are increased. A logic LSI is permitted to have redundancy to flexibly cope with design changes. This affords reduction in develop period and develop costs.

Semiconductor integrated circuit and method of designing same

A semiconductor integrated circuit, which can process n-bit (n is an integer, n&gt;1) instructions or data at a time, has queues for storing instructions or data of m (m&gt;1) times n bits received from an external memory through an instruction bus or a data bus. Therefore, it is possible to achieve an improvement in performance of the semiconductor integrated circuit and further to provide a low-priced semiconductor integrated circuit.

Semiconductor integrated device with an improved performance

A register circuit an arithmetic circuit a register circuit and a logic circuit form a bit slice cell corresponding to a path of propagation connecting the circuits in this order. Similarly, an arithmetic circuit register circuits and a logic circuit form a bit slice cell and an arithmetic circuit register circuits and a logic circuit form a bit slice cell. The bit slice cells are arranged generally in parallel to form a bit slice circuit which prevents redundant lines for connecting the functional circuits, whereby the bit slice circuit is developed in a short period without a decreased degree of integration and prolonged delay time.

Integrated circuit device and method of designing same

By the disclosed apparatus, the method and the electronic circuit device employing the disclosed apparatus, a configurable semiconductor integrated circuit device is manufactured in a reduced time. A regular logic input/output terminal (6) of a configurable semiconductor integrated circuit device (FPGA) (1) is connected to a data processing apparatus (52) through an interface circuit (51). On a magnetic disk (55), logic function specifying basic data are stored which define basic logic functions which are attainable with circuit diagram data and by the FPGA (1). The data processing apparatus (52) generates logic function specifying final data based on the circuit diagram data while utilizing basic logic operations of the FPGA (1) which is loaded with a logic. Since the basic logic operations of the logic-loaded FPGA (1) are used in generating the logic function specifying final data, the FPGA (1) is manufactured in a reduced time.

Method of manufacturing a semiconductor integrated circuit device, and

A method of manufacturing a plurality of integrated circuit devices includes the steps as follows. First, a predetermined plurality number of bonding pads (11, 21) in a predetermined geometry are formed on the surface of each of a plural number of substrate (10, 20). Next, circuits (12, 22) having different signal processing functions respectively are formed in regions of the substrates (10, 20) not occupied by the bonding pads (11, 21), and then, input/output terminals of the circuits (12, 22) are interconnected to respective ones of the bonding pads (11, 21). According to such a manufacturing method of integrated circuit devices, it is possible to employ common devices for wafer test and the same packages for incorporating, and thus reduce production cost and development cost, in case of small quantity production of various types.

Integrated circuit device having a geometry to enhance fabrication and

In designing a layout of a semiconductor integrated circuit device having a large scale circuit block and logic circuit elements provided together, a power supply connecting line is formed rectilinearly to increase the integration density, reduce power supply noise and achieve automation of layout and interconnection. The semiconductor integrated circuit device includes one large scale circuit block and a plurality of logic circuit elements. VDD and GND annular power supply interconnecting lines are provided to surround the large scale circuit block. The annular power supply interconnecting lines extending in the lateral direction are divided into two lines to be disposed, respectively. Connection of the logic circuit elements and the annular power supply interconnecting lines are made by rectilinear VDD and GND power supply branch interconnecting lines.

Semiconductor integrated circuit having annular power supply with plural

Test data applied serially from a data input terminal 6 is bypassed by a selecting circuit in modules that are not the object of testing and applied to a scan path in modules that are the object of testing. Test data is applied to the control point of the functional module from the scan path, and test result data provided from the observation point of the functional module and fetched by the scan path. The scan path shifts the fetched test result data to provide serially from a data output terminal 7. Each of selecting means 5a-5c operates in response to the selecting data held in the corresponding selecting data holding/propagating circuits 9a-9c. These selecting data holding/propagating circuits 9a-9c shift and hold selecting data applied serially from a data input terminal 10.

Scan path system and an integrated circuit device using the same

Three shift path circuits (10', 20', 30') each comprising a bypass circuit are connected in series between a test data input (TDI) and a test data output (TDO). Each shift path circuit constitutes a design definition test data register connected to a circuit to be tested. Design modification of a testing circuit can be minimized by selectively operating the bypass circuit provided in a shift path circuit, even if there is circuit modification in the circuit to be tested. The period of time required for testing circuits to be tested is reduced.

Semiconductor integrated circuit device comprising scan paths having

The multiplication circuit is formed in such a manner that the intermediate sums of partial products are divided into a lower places group and a higher places group and the operations for obtaining the products of the lower places group alone of the intermediate sums already found are carried out parallel to the processing for obtaining the higher places group of the intermediate sums to obtain the higher products thereafter, noting to the fact that the intermediate sums of partial products are found sequentially from lower places to higher places. By adopting such an arrangement, the operations for obtaining the higher places group of the intermediate sums can be processed in parallel with the operations for obtaining the products of the lower places group of the intermediate sums already found, and the higher products are found thereafter. Therefore, the time required for the former-stage processing and that required for the latter-stage processing can be made more uniform.

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Hyogo, Japan

Kazuhiro Sakashita