Nec Corporation

Kazuhiro Okabe

Isami Sakai

In an apparatus for clock tree synthesis allocation wiring, the wiring is appropriately conducting while minimizing the wiring cost and power consumed in operation. A first file stores therein information of operating frequencies of clock lines. Second file stores therein information of a maximum capacity allowed for a clock buffer for each operating frequency obtained according to restriction of electro-migration. A maximum capacity determining device determines a maximum capacity allowed for an operating frequency according to information of the operating frequency from the input device, information of the operating frequencies stored in the first file, and information of the maximum capacity stored in the second file. A tool for clock tree synthesis allocation wiring conducts wiring by assuming the maximum capacity to be a limiting value of a maximum capacity which can be added to each clock buffer.

Apparatus for and a method of clock tree synthesis allocation wiring

A process for fabricating a semiconductor device comprising the steps of forming a gate insulation layer on a first conductive type semiconductor substrate, forming a polycrystalline silicon layer on the gate insulation layer, and selectively removing the polycrystalline silicon layer to form a gate electrode and a direct contact electrode. The process also includes a step of forming a photoresist mask masking the direct contact electrode at least at the side opposing the gate electrode, and performing ion implantation of a second conductive type impurity for forming an impurity diffused layer at both sides of the gate electrode. The direct contact electrode and the impurity diffused layer are electrically connected by a conductive layer covering the surface of one of the impurity diffused layer and the side surface of the direct contact electrode.

Process for fabricating complementary field effect transistors having a

Disclosed is an improved metal oxide-semiconductor field-effect transistor having two diffused regions extending apart from under one and the other edge of the gate in the opposite directions, at least one of the diffused regions being composed of a first leastdoped, short section, a second lightly-doped, short section, and a third heavily-doped, long section. Either diffused region may be used as drain. The series-connection of least and lightly-doped sections of the same longitudinal size or depth improves the current driving capability of the semiconductor device. Also, methods of making such MOSFETs are disclosed.

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Tokyo, Japan

Kazuhiro Okabe