Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Kazuhiro Okabayashi

Minoru Okamoto

Shinichi Marui

Masayuki Yamasaki

Yukihiro Sasagawa

Ryutaro Yamanaka

Takao Yoshida

A panel control device includes a programmable array. This programmable array operates in accordance with a configuration code and includes a plurality of first-class elements and at least one second-class element. This provides a panel control device requiring a small circuit area, being suitable for system-on-chip (SoC) mounting, and driving a liquid crystal display device having various specifications also in the future.

Panel control device and panel control system

A semiconductor integrated circuit comprising a plurality of memory circuits; a BSIT circuitoperable to output test vectors; and one or more register circuit(s)each allocated on a signal line that transmits test vectors output by the BIST circuitto any of the memory circuits, and operable to sequentially transfer the test vectors to an adjoining macro cell in accordance with the clock signals.

Semiconductor integrated circuit and BIST circuit design method

A method of configuring an information processing system according to the present invention, in an information processing system for realizing one or a plurality of applications, comprises, a step of modeling all of the applications for each certain process level and inputting the models, a step of inputting parameters representing invariability for the inputted models, a step of using the models of the applications and the parameters representing invariability as inputted information and comparing the parameters representing invariability to a boundary condition, and a step of allocating one of the application models to programmable logic and another of the application models to an exclusive-use hardware based on a result of the comparison.

Method of configuring information processing system and semiconductor integrated circuit

A first processor, a second processor, a memory and a clock supply unit are integrated together on a single chip. The first processor operates synchronously with a first internal clock signal. The second processor operates synchronously with a second internal clock signal. The memory operates synchronously with a third internal clock signal. The clock supply unit generates three clock signals, which are in phase with each other, from an external clock signal and supplies those clock signals as the first, second and third internal clock signals. The first and second processors share the memory via a data bus. Each of the processors has an internal reset signal.

Apparatus for controlling and supplying in phase clock signals to components of an integrated circuit with a multiprocessor architecture

In a circuit blockto be an object of power-off, voltage detecting circuitsandare disposed near power supply terminalsand, respectively, and voltage detecting circuitsandare disposed at given positions far from the terminalsand, respectively, on power linesandof two electric-supply systems. The voltage detecting circuits are each made of MOS transistors only. At turning on the power from a power supply circuitagain, after all the voltage detecting circuits have detected arrival of power-supply voltages at a predetermined potential, a reset signal generating circuitstops the input of a reset signal to the circuit blockAccordingly, since the reset state is stopped after the arrival of the power-supply voltages at the predetermined voltage, a semiconductor integrated circuit is initialized normally. This provides a semiconductor integrated circuit capable of generating a power-on reset signal appropriately.

Semiconductor integrated circuit and its reset method

To enable high-speed CRC operation and flexible use of various generating polynomials without causing significant increase in circuit scale, the CRC operation unit uses circuits generally provided for a DSP and some additional circuits. The CRC operation unit includes: a generating polynomial supply section having a first general register for storing an arbitrary generating polynomial and a selector for selectively outputting the generating polynomial or data of which all bits has a value of 0; an operation data supply section having a memory, a shift register, a second general register, and a barrel shifter, for outputting operation data for CRC operation based on transmitting/receiving data; an operation section for performing CRC operation using the generating polynomial output from the generating polynomial supply section and the operation data output from the operation data supply section; and an operation instruction execution control section for controlling the operations of the above sections.

CRC operation unit and CRC operation method

A coding apparatus includes shift register, input register and logical operation section. The shift register performs bit shifting on an input bit sequence and stores one bit of the input bit sequence after another. The input register stores coefficients of terms on respective orders of a generator polynomial. The logical operation section obtains logical products of the respective bits stored on the shift register and associated bits stored on the input register and a logical product of each one bit input to the shift register and an associated bit stored on the input register so that the earlier a bit of the input bit sequence was input, the higher-order one of the coefficients in the terms of the polynomial the input bit is associated with. Next, the logical operation section derives an exclusive logical sum of the products and then outputs the sum as a bit of a code sequence.

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Osaka, Japan

Kazuhiro Okabayashi