Texas Instruments Corporation

Kazuhiro Ohara

Hiroshi Miyaguchi

Masafumi Yugami

Yuji Yaguchi

An EDTV application utilizing a Synchronous Vector Processor (SVP) includes the operation whereby noise is reduced in the operation to demodulate the chroma signal. Initially, the NTSC composite video is separated into the luminance (Y) and the chroma (C) signals by a Y/C separator algorithm (272). The chroma signal is then processed through a colorburst calculation algorithm (290). During the colorburst calculation, the phase of the colorburst signal is determined by processing the chroma signal through a phase detector (416) to provide the phase components S.sub.i and M.sub.i. Both signals are cyclic signals and are processed in accordance with a majority noise reduction algorithm. The majority noise reduction algorithm is operable to sample a given portion of one of the cycles in the cyclic signal and also sample corresponding portions in adjacent cycles both prior to the present portion and preceding the present portion. A decision as to a logic state of the present portion is made by comparing all of the logic states of the sampled portions and forcing a select portion to the logic state of the majority of the sampled portions. This is then input to a phase shift circuit (414) and then to a demodulator (412) to adjust the phase thereof and output demodulated chroma.

Method and apparatus for noise reduction of cyclic signal by selecting

A method of measuring the motion in video image data for a pixel which uses both field-difference and frame-difference motion values to generate a motion value having increased accuracy. Image data (806) from the same pixel in a prior row of the same field (906) is compared to image data (808) from the same pixel in the prior row of the prior frame (908), and the absolute value of the difference is compared to the absolute value of the difference in image data (802) from the same pixel in a following row of the same field (902) and image data (804) from the same pixel in the following line of the prior frame (904). The minimum of these two values is the minimum frame-difference motion value which is input into a logical mixer. Also input into the logical mixer is the minimum field-difference motion value which may be determined by comparing data (802, 806) from the same pixel of an adjacent line of the same field (902, 906) with image data (810) from the same pixel of the same line of the prior field. The average of image data (810) from the same pixel of the same line of the prior field and image data (812, 814) from the same pixel of two rows prior or two rows after of the prior field (912, 914) may be used instead of image data (810) from the same pixel of the same line of the prior field alone, to increase the accuracy of the measurement.

Motion detection using field-difference measurements

A method for operating a scan-line video processor that allows for vertical scaling with no additional memory in a display system and extracts more SVP instructions in vertical down scaling applications. The input and output sync periods of the SVP (16) are controlled such that the SVP (16) produces output lines of interpolated data that is a vertical scaling factor of the input lines. The data is then sent to a memory (24) to correct for centering and time base changes in the interpolated data. Finally, the data is sent to a display device, such as a CRT or a spatial light modulator.

Method for vertical imaging scaling

A single-instruction multiple-data (SIMD) processor (10) that incorporates features for horizontal scaling of video data. The processor (10) has a data input register (11) that is operable to store input data word in sequential locations in the data input register (11) and transfer the input data words to an array of processing elements. The processor (10) also has an output data register (16) operable to receive data output words from the array of processing elements and to output said data output words from sequential locations of said output data array. An input skip signal input to the processor causes a sequential data write operation to skip a location of the input data register while an output skip signal to the processor causes a sequential data read operation to skip a location of the output data register.

Single-instruction multiple-data processor with input and output

A synchronous vector processor (SVP) device (102) has a plurality of processing elements (150) which are comprised of an RF1 register (166), an ALU (164) and an RF0 (158). The processing elements are operable to be disposed between the data input register DIR (154) and the data output register (DOR) (168) to process data therebetween. Data is received in DIR (154), transferred to the processing elements (150), processed and then output to the DOR (168). A fast response clock operates the DIR (154) such that the jitter on the input signal is tracked. The Read clock on the DOR (168) is a stable clock. Data transferred between the DIR (154) and the DOR (168) is buffered in an elastic buffer to provide a time based compensation (TBC). To facilitate this, a buffer is implemented in either the RF1 (168) or the RF0 (158). A dual global rotation pointer is provided to generate two pointers that are asynchronous. The first pointer allows data to be transferred to the buffered area from/to the ALU (164) and the second pointer allows data to be transferred to the DOR (168) from the RF0 (158) or from a DIR (154) to the RF1 (166). A hardware interrupt is provided to perform this asynchronous transfer.

Apparatus and method for synchronizing data transfers in a single

An automatic color control and chroma killer circuit 3 and video processing system is provided that is capable of controlling an amplitude of a color signal and of performing a killer function with a simple construction without using a divider and/or vertical filter. The ACC/ACK device includes ACC and ACK circuitry which may be selectively enabled with operating signals to a selector 27. When the selector 27 enables amplitude detector 25, the amplitude detector 25 detects amplitude of the input color signal and a coefficient controller 26 compares it with a killer level. If the input color signal fails to meet the killer level then the coefficient controller 26 controls a coefficient generated by the coefficient generator 22 to perform a killer operation. The ACC operation and circuitry is thereby ACK controlled until an input color signal meets or exceeds the killer level. When the selector 27 enables the multiplier circuit 11 according to an operating signal input, the input color signal is ACC controlled by the multiplier circuit 11, and amplitude detector 21, a coefficient generator 22, a coefficient memory 23 and a delay circuit 24.

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Chiba, Japan

Kazuhiro Ohara