Kabushiki Kaisha Toshiba

Hitachi, Ltd.

Hitachi-lg Data Storage, Inc.

Kazuhiro Oda

Tokinori Furuichi

Naoyuki Hamanishi

Seiji Inaba

Zdzislaw Czarnul

Hiroyuki Hayashi

Naomi Nomura

Yuji Hirai

Gohshi Jin

Hiroyuki Minemura

Koichi Watanabe

Shigeo Ohashi

Yoshiaki Yamauchi

Hirotomo Ishii

Harushige Nakagaki

Makoto Ibe

Hiroyuki Toyoda

Hideo Suenaga

Ryuichi Koike

Shinji Nakatsuka

Mitsunori Kobayashi

An echo cancellation circuit in a full duplex two-way communication system comprising: an input/output terminal; a subtractor having a positive and a negative input terminals, in which a first transmission signal is inputted to the negative input terminal as a pseudo echo signal, the first transmission signal is inputted through an output buffer to the positive input terminal as an echo signal, the pseudo echo signal inputted to the negative input terminal is subtracted from the echo signal inputted to the positive input terminal; and a result of the subtraction is outputted; and an echo cancellation error reducing unit having a D/A converter at an input side or an output side of the subtractor.

Echo cancellation circuit

An objective of the present invention is to enhance reliability of recorded data by preventing deterioration of OPC (Optimum Power Calibration) accuracy due to an influence of inter-layer interference in an optical disk device capable of writing in a multilayer optical disk. Aiming at the objective, a relationship between asymmetry and a signal modulation depth, which are measured by use of a standard driver is referred, and thereby an offset caused by a device, a disk, a writing state of another layer and the like is compensated. Thus, OPC is executed.

Writing method and optical disk device

In a recording disk apparatus, a pickup element and an electric element for at lease one of supplying an electric power to at least one of a recording disk driving motor and the pickup and processing a signal to be recorded into the recording disk and/or the signal read from the recording disk are prevented from overlapping each other as seen in a thickness direction of the recording disk to restrain a thermal conduction between the pickup element and the electric element so that a thermal conduction restraining area extending along an imaginary directional line crossing an imaginary straight line passing the pickup element and the electric element as seen in the thickness direction is formed between the pickup element and the electric element as seen in the thickness direction.

Recording disk apparatus having regions of constrained thermal conduction

The present invention provides a single information recording and reproducing apparatus that is used to record data to multiple disks that are to be recorded on using different wavelengths. More specifically, the present invention provides an apparatus that accurately discriminates disk types while preventing disk damage and accidental recording of data during the disk type discrimination operation. The disk type is determined using the intensity of light reflected from the disk. Information is encoded using an encoder corresponding to the disk type. The resulting signal is used to drive a laser corresponding to the disk type, and information is recorded.

Information recording and reproducing apparatus and disk discrimination method thereof

The apparatus for converting a differential input voltage to two fully balanced output currents is achieved by providing a common mode control circuit of a simplified circuit construction to an operational transconductance amplifier. The apparatus includes an operational transconductance amplifier that is comprised of an OTA input section for converting two input voltages of the differential input voltage to a pair of interim output currents and an OTA output section for converting the interim output currents to the output currents, and a common mode controlling circuit for providing a control voltage to the OTA. The common mode control circuit is comprised of a substantially same circuit construction as the OTA output section and generates two output control currents based on the interim output currents from the OTA input section and the two output control currents from the common mode control circuit are summed and kept to be substantially zero in order to control the output currents from the OTA output section fully balanced.

Apparatus and method for converting differential voltage to fully balanced currents

In an operational amplifier constituted by a differential stage which receives two input signals IN- and IN+ and outputs a signal NGP corresponding to the potential difference, a level shift stage which receives the signal NGP and outputs a level-shifted signal NGN, and an output stage which receives the signals NGP and NGN and outputs a signal OUT obtained by amplifying the potential difference between the two input signals, the level shift stage is formed from a DDA. Letting A1, A2, and A3 be the gains of the DDA, the input signal NGP, output signal NGN, and bias voltages VBP and VBN have a linear relation given by A3{A1(VBN-NGN)-A2(VBP-NGP)}=NGN. This maximizes the current drivability of a transistor TN1 on the output stage and controls the punch-through current flowing between transistors TP1 and TN1.

Operational amplifier

In a comparator circuit comprised of a feedback amplifier and a differential amplifier AMP1, the feedback amplifier includes input transistors Tr1 to Tr4. Gates of the transistors Tr1 and Tr2 are respectively inputted with first and second inverted inputs, and gates of the transistors Tr3 and Tr4 are inputted with first and second non-inverted inputs. First ends of current paths of the transistors Tr3 and Tr4 are connected in common, and ends of current paths of transistors Tr1 and Tr2 are connected in common. Second ends of the current paths of the transistors Tr1 to Tr4 are connected in common to a constant current source. The first and second inverted inputs are supplied with a reference voltage, and the first and second non-inverted inputs are respectively supplied with the non-inverted and inverted outputs of the differential amplifier AMP1. A signal from a connection point common to the first ends of the current paths of the transistors Tr3 and Tr4 is supplied as a feedback output to the differential amplifier AMP1 to control operation of the differential amplifier AMP1. The timing when feedback is performed to stabilize the operating point of the differential amplifier AMP1 is the timing when the non-inverted and inverted outputs of the differential amplifier AMP1 have a small potential difference therebetween or are substantially equal to each other.

Comparator circuit

An method to prevent excessive heat generation of the pickup actuator from occurring when a disk has a large eccentricity or planar vibration in a high-speed disk reproducing apparatus using an optical pickup. The disk reproducing apparatus has a status determining arrangement for monitoring a present actuator drive state, an analyzing arrangement for analyzing an output signal of the status determining arrangement, and disk rotational speed switching control arrangement for selecting disk reproducing speeds according to a control signal of the identification means, thereby lowering the reproducing speed when the eccentricity or planar vibration is large. Such invention prevents heat generation of the pickup actuator from occurring because high-speed reproduction can be performed when the eccentricity or planar vibration is small, and reproduction speed can be automatically reduced when the eccentricity or planar vibration is large.

Disk reproducing speed control method and a disk reproducing apparatus

The present invention provides a D/A converter which has a small area in the chip, a linear current output and a high-speed operation. Each of resistors R.sub.11 -R.sub.n1 in a resistor train 11a is composed of four MOS transistors which are connected in parallel with each other and each of resistors R.sub.12 -R.sub.n2 in a resistor train 11b is composed of four MOS transistors which are connected in parallel with each other. Between the connecting nodes of the resistor trains 11a, 11b, MOS transistors ST.sub.11, ST.sub.12, ST.sub.13, ST.sub.14 -ST.sub.n1, ST.sub.n2, ST.sub.n3 and ST.sub.n4 which serve as switches and resistors are connected. All the MOS transistors have the same conductive type and size. Gate control signals C.sub.11 -C.sub.n1 ; C.sub.12 -C.sub.n2 turn MOS transistors ON but each of them has a different voltage value. A current difference between the output terminals Za and Zb is converted into a voltage difference by an operational amplifier or the like.

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Yokohama, Japan

Kazuhiro Oda