Fujitsu Corporation

Kazuhiro Nunomiya

Toshiya Uchida

Hiroko Douchi

The present invention relates to a level interface circuit, which receives a first interface input signal having a level H and a level L, as fixed potentials, and a first reference level which is midway therebetween, and a second interface input signals having a level H, a level L and a second reference level determined in accordance with a power source voltage, and which compares an input signal of one of said first and second interface input with one of said first and second reference level signal and generates an output signal, said level interface circuit further comprising: a first and a second transistors, having a common source connection, for receiving said input signal and said reference level signal at respective gates; a current source transistor connected to said source of said first and said second transistors; a load circuit connected to drains of said first and said second transistors; a voltage control transistor provided between said load circuit and said power voltage source; and a voltage controller for determining whether said input signal corresponds to said first or said second interface input, and increasing or reducing an impedance of said power control transistor in accordance with the determination.

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Kawasaki, Japan

Kazuhiro Nunomiya