Elpida Memory, Inc.

Ps4 Luxco S.a.r.l.

Other

Kazuhiro Nojima

Kiyonori Oyu

Yoshihiro Takaishi

Kensuke Okonogi

A semiconductor pillar which has a first conductivity type and protrudes from a semiconductor substrate, is formed. A bottom diffusion layer having a second conductivity type is formed in the semiconductor substrate around a bottom of the semiconductor pillar. A gate insulator film which covers a side surface of the semiconductor pillar, is formed. A gate electrode which covers the gate insulator film, is formed. A top diffusion layer having the second conductivity type is formed at a top portion of the semiconductor pillar. The top diffusion layer including a semiconductor body is formed by an epitaxial growth which contains an impurity.

Method of manufacturing a pillar-type vertical transistor

A crystal material lattice strain evaluation method includes illuminating a sample having a crystal structure with an electron beam in a zone axis direction, and selectively detecting a certain diffracted wave diffracted in a certain direction among a plurality of diffracted waves diffracted by the sample. The method further includes repeating the illuminating step and the selectively detecting step while scanning the sample, and obtaining a strain distribution image in a direction corresponding to the certain diffracted wave from diffraction intensity at each point of the sample.

Method and system of evaluating distribution of lattice strain on crystal material

A semiconductor device includes a first island and a first electrode. The first island includes a first semiconductor region, a first insulation region, and a first insulating film. The first semiconductor region has first and second side surfaces adjacent to the first insulation region and the first insulating film, respectively. The first electrode is adjacent to the first insulation region and the first insulating film. The first insulating film is between the first electrode and the first semiconductor region.

Semiconductor device and method of forming the same

A semiconductor device is provided, which includes an N well having a peak concentration of 2E+17 atom/cmor more in the range of 0.2 to 1 &#x3bc;m depth from the surface of a P-type semiconductor substrate, and a region provided below the N well, the region containing P-type impurities with higher concentration than concentration of electrons.

Semiconductor device

A semiconductor structure may include, but is not limited to: a semiconductor substrate; a first semiconductor structure extending upwardly over the semiconductor substrate; and a second semiconductor structure extending upwardly over the semiconductor substrate, the first and second semiconductor structures being aligned in a first &#x3c;100&#x3e; direction.

Semiconductor device including a pillar MOS transistor

A method of manufacturing a semiconductor device includes forming a gate electrode material that covers a gate insulating film formed on each of side surfaces of first and second silicon pillars, wherein a film formation amount of the gate electrode material is controlled so that a first part with which the side surface of the first silicon pillar is covered via the gate insulating film does not contact with a second part with which the side surface of the second silicon pillar is covered via the gate insulating film. The method further includes: forming a mask insulating film that covers the first and second parts and fills a region between the first and second parts; and etching the gate electrode material using the mask insulating film as a mask, thereby forming gate electrodes with which the side surfaces of the first and second silicon pillars are covered via the gate insulating film, respectively and a conductive film electrically connecting the gate electrodes to each other.

Manufacturing method of semiconductor device having vertical transistor

A semiconductor device includes: a semiconductor substrate; a silicon pillar provided perpendicularly to a main surface of the semiconductor substrate; a gate dielectric film that covers a portion of a side surface of the silicon pillar; an insulator pillar that covers remaining portions of the side surface of the silicon pillar; a gate electrode that covers the silicon pillar via the gate dielectric film and the insulator pillar; an interlayer dielectric film provided above the silicon pillar, the gate dielectric film, the insulator pillar, and the gate electrode; and a gate contact plug embedded in a contact hole provided in the interlayer dielectric film, and in contact with the gate electrode and the insulator pillar. A film thickness of the insulator pillar in a lateral direction is thicker than a film thickness of the gate dielectric film in a lateral direction.

Semiconductor device having vertical transistor, manufacturing method thereof, and data processing system

To provide a semiconductor memory device comprising a plurality of silicon pillars arranged in a matrix, whose sidewalls are provided with gate electrodes with gate insulating films interposed between the silicon pillars and the gate electrodes and whose top ends are electrically connected to memory elements, and a bit line and a word line provided between the silicon pillars so as to be orthogonal to each other. The bit line is electrically connected to a bottom end of the silicon pillars on both sides of the bit line in alternate rows, and the word line is electrically connected to a gate electrode formed on a sidewall of the silicon pillars on both sides of the word line in alternate columns.

Semiconductor memory device and manufacturing method thereof

A method of manufacturing a semiconductor device includes forming silicon pillaron substrate, forming a protective film which covers an upper end portion and a lower end portion of a side surface of silicon pillar, forming a constricted portion by anisotropic etching in a portion of the side surface of silicon pillarwhich is not covered with the protective film after forming the protective film, removing the protective film after forming the constricted portion, forming gate oxide filmwhich covers the side surface of silicon pillarin which the constricted portion is formed, and forming gate electrodewhich covers gate oxide film

Growing community of inventors

Tokyo, Japan

Kazuhiro Nojima