Sanyo Electric Co., Ltd.

Semiconductor Components Industries, LLC

Sanyo Semiconductor Co., Ltd.

Kazuhiro Nakamuta

Iwao Honda

Takashi Kuroda

A stream data reproducing system comprising: an input buffer configured to accumulate stream data input from a stream source; a decode circuit configured to decode the stream data accumulated in the input buffer by predetermined processing unit to generate decode data; an output buffer configured to output the decode data after accumulation thereof; a transfer memory cell configured to store the stream data accumulated in the input buffer and the decode data generated in the decode core circuit; and a data transfer control circuit configured to control transfer of the stream data by the processing unit from the input buffer to the transfer memory cell, and transfer of the decode data by the processing unit from the transfer memory cell to the output buffer.

Stream data reproduction system

A memory access apparatus reading data from a memory, the memory including a terminal that address information is input to, a terminal that a clock signal changing at a predetermined cycle is input to, a terminal that a read command is input to, and a terminal that outputs data stored at an address identified by the address information at a timing of the clock signal changing from one level to the other level in accordance with the read command, the memory access apparatus comprising: an address information output unit that outputs the address information and the read command at a first timing of the clock signal changing from the one level to the other level; and a read data storage unit that stores data output from the memory at a second timing after the first timing of the clock signal changing from the one level to the other level, the read data storage unit storing the data at a third timing after the second timing of the clock signal changing from the one level to the other level.

Growing community of inventors

Gunma-ken, Japan

Kazuhiro Nakamuta