Nec Electronics Corporation

Kabushiki Kaisha Toshiba

Nec Corporation

Kazuhiro Nakajima

Masaharu Mizuno

Kenji Yamamoto

Tokihiro Umemura

Noriko Kawakami

Tomotsugu Ishizuka

Tomonari Aoki

A universal logic module includes: a first inverter outputting an inverted input signal to an output terminal through a first transfer gate, the inverted input signal having an inverted level of an input signal provided from a first input terminal; and a second inverter outputting an inverted logic signal to the output terminal through a second transfer gate, the inverted logic signal having an inverted level of a first logic signal. The first input terminal is connected to one of a power supply line and a ground line. An input of the first transfer gate is directly connected to the other of the power supply line and the ground line. The first and the second transfer gates are complementarily turned on/off according to a level of a second logic signal. A result of a logical operation between the first and the second logic signals is outputted from the output terminal.

Semiconductor device having universal logic cell

A ring oscillator for a test apparatus and method for verifying fabrication of transistors in an integrated circuit on a die under test is implemented. The ring oscillator is fabricated on the die and includes a positive feedback loop between a circuit output terminal and a feedback input terminal. The feedback loop includes a plurality of delaying stages connected in cascade. A transfer gate is coupled to each delaying stage. Each of the transfer gates includes a pair of transistors of the first and second conductivity types connected in parallel. The ring oscillator is operable to provide a first oscillator output signal during a first test mode when the transistors of the first conductivity type are ON and the transistors of the second conductivity type are OFF. The ring oscillator is operable to provide a second oscillator output signal during a second test mode when the transistors of the first conductivity type are OFF and the transistors of the second conductivity type are ON. The ring oscillator is operable to provide a third oscillator output signal during a third test mode when the transistors of the first conductivity type are ON and the transistors of the second conductivity type are ON.

Test method and apparatus for verifying fabrication of transistors in an integrated circuit

A universal logic module that may have a reduced off-leak current in universal logic cells () not used as logic circuits has been disclosed. A universal logic module may include universal logic cells () that may be formed with a second wiring for connecting universal logic cells () from a base configuration formed with a first wiring. Unused universal logic cell () may include transistors in basic cells (A to E) that are non-connected to a power supply (VDD) and/or a ground potential (VSS). Furthermore, unused universal logic cell () may include transistors in basic cells (A to E) that may provide a capacitor between a power supply (VDD) and a ground potential (VSS). In this way, off-leak current may be reduced and noise on a power line and/or a ground line may be reduced.

Universal logic module and ASIC using the same

A power control device includes an electric power storage device connected across a power supply line for a load and including at least one electric double layer capacitor (EDLC) bank and a secondary battery combined with the EDLC bank, the EDLC bank including a plurality of parallel-connected rows of EDLC unit cells, each of the rows including a plurality of series-connected EDLC unit cells, and a control device controlling the electric power storage device so that when an input power to the electric power storage device is interrupted, the EDLC bank supplies electric power to the load for an initial period of the power interrupt and subsequently, the secondary battery supplies electric power to the load.

Power control device with electric double layer capacitor unit cells

A phase comparator is disclosed that can provide a phase comparison result at high speed that essentially does not vary according a power source voltage, ambient temperature and/or manufacturing process conditions, or the like. A phase comparator ( ) may include one-shot pulse generating units ( and ) that output one-shot pulses according to input data signal DAT and clock signal CLK, respectively. An R-S flip-flop ( ) can receive one-shot pulses from one-shot pulse generating units ( and ) at set and reset inputs, respectively. An output flip-flop ( ) can select between an output signal of R-S flip-flop ( ) and a delay signal &ldquo;a8&rdquo; generated from input data signal DAT, and latch such a result according to a delayed clocks signal CLK.

Phase comparator

A tree wiring distributes an externally supplied clock signal to a plurality of first clock buffers. Routes of the tree wiring are designed so that the externally supplied clock signal can reach the plurality of first clock buffer substantially at the same time. The plurality of first clock buffers are connected to all intersections existing on a mesh wiring in one to one correspondence. The plurality of first clock buffers supply a clock signal supplied thereto through the tree wiring, to the mesh wiring. The mesh wiring protrudes from the intersections thereof which face toward outside by a predetermined length in order to keep load imposed on the plurality of first clock buffers uniform. A plurality of second clock buffers are connected to the mesh wiring, and supply clock signals supplied thereto from the plurality of first clock buffers through the mesh wiring, to a plurality of circuit elements.

Clock signal distribution circuit

In a method of designing a signal distribution circuit, a plurality of circuit patterns of buffer circuits and patterns of wiring lines are arranged and connected to have a tree structure. A total delay time from an input of the buffer circuit in the highest layer of the tree structure to an output of each of the buffer circuits in the lowest layer of the tree structure is calculated. Each of the plurality of circuit patterns of the buffer circuits is selectively substituted by one of substitution patterns of substitution buffer circuits such that the total delay times fall within a predetermined range. All the outputs of the buffer circuits in the lowest layer of the tree structure are connected.

Method of designing signal distribution circuit and system for supporting the same

Methods of designing and manufacturing a semiconductor device are disclosed in order to reduce the manufacturing cost of the semiconductor device, and to easily realize a high-speed circuit by reducing wiring capacity. A maximum pitch of wiring of the wiring layers is determined under a condition that power consumption of the semiconductor chips at a predetermined operating frequency is equal to or less than a predetermined value, and the width and spacing of wiring of the wiring layers and the width of each contact for mounting the semiconductor chips are determined based on the determined wiring pitch the semiconductor device is manufactured by using a mask and a manufacturing process by which the determined pitch and width of wiring are realized.

Growing community of inventors

Kanagawa, Japan

Kazuhiro Nakajima