Seiko Epson Corporation

Kazuhiro Maekawa

Takashi Kumagai

Satoru Kodaira

Satoru Ito

Hisanobu Ishiyama

Junichi Karasawa

Takashi Fujise

Noboru Itomi

Masahiko Moriguchi

Shuji Kawaguchi

Katsuhiko Maki

Takayuki Saiki

Hiroyuki Takamiya

Motoaki Nishimura

Hironori Kobayashi

Haruo Kamijo

Kinya Matsuda

Isamu Moriya

A rectifier circuit includes: a first input line to which a first alternating-current voltage is supplied and that is wired along a first direction; a second input line to which a second alternating-current voltage is supplied and that is wired along the first direction on a second direction side of the first input line; a first output line that is configured to output a first rectified voltage and is wired along the second direction; a second output line that is configured to output a second rectified voltage and is wired along the second direction on a first direction side of the first output line; a first rectifier element that is arranged corresponding to an intersection of the first input line and the first output line; a second rectifier element that is arranged corresponding to an intersection of the second input line and the first output line; a third rectifier element that is arranged corresponding to an intersection of the first input line and the second output line; and a fourth rectifier element that is arranged corresponding to an intersection of the second input line and the second output line.

Rectifier circuit and power reception control device

An integrated circuit device includes first to Nth circuit blocks CBto CBN, a first interface region disposed along a fourth side and on the Dside of the first to Nth circuit blocks CBto CBN, and a second interface region disposed along a second side and on the Dside of the first to Nth circuit blocks CBto CBN. A local line LLG formed using a wiring layer lower than an Ith layer is provided between the adjacent circuit blocks as at least one of a signal line and a power supply line. Global lines GLG and GLD formed using the Ith or higher wiring layer are provided along the direction Dover the circuit block disposed between the nonadjacent circuit blocks as at least one of a signal line and a power supply line.

Integrated circuit device and electronic instrument

An integrated circuit device includes at least one data driver block for driving data lines, a plurality of control transistors TCand TC, each of the control transistors being provided corresponding to each output line of the data driver block and controlled by using a common control signal, and a pad arrangement region in which data driver pads Pand Pfor electrically connecting the data lines and the output lines QLand QLof the data driver block are disposed. The control transistors TCand TCare disposed in the pad arrangement region.

An integrated circuit device includes first and second transistors NTrand PTrpush-pull connected between first and second power supply lines and outputting a voltage of one of the first and second power supply lines to a connection node ND by a charge-pump operation, and a pad PD electrically connected with the connection node ND and electrically connected with a flying capacitor, to which a given voltage is applied at one end, at the other end of the flying capacitor. The pad PD is disposed in an upper layer of at least one of the first and second transistors NTrand PTrso that the pad PD overlaps part or the entirety of at least one of the first and second transistors NTrand PTr

An integrated circuit device includes a pad PDx and an electrostatic discharge protection element ESDx formed in a rectangular region and electrically connected with the pad PDx. The pad PDx is disposed in an upper layer of the electrostatic discharge protection element ESDx so that an arrangement direction of the pads is parallel to a long side direction of the region in which the electrostatic discharge protection element ESDx is formed, and the pad PDx overlaps part or the entirety of the electrostatic discharge protection element ESDx.

A driver circuit which drives a source line of an electro-optical device includes a source line driver section which supplies a grayscale voltage corresponding to grayscale data to the source line, a source output switch section which short-circuits the source line and a common line connected with a capacitor before the source line driver section drives the source line, and a charge recycle control section which controls the source output switch section. The charge recycle control section determines whether or not to short-circuit the source line and the common line in source line units based on the grayscale data and polarity of a common electrode voltage supplied to a common electrode opposite to a pixel electrode of the electro-optical device. The source output switch section short-circuits the source line and the common line based on the determination result of the charge recycle control section.

Driver circuit, electro-optical device, and electronic instrument

A display driver includes a common electrode charge storage switch provided between a first capacitor element connection node to which one end of a first capacitor element can be connected and a common electrode voltage output node to which a voltage of a common electrode opposite to a pixel electrode of an electro-optical device through an electro-optical material is supplied, a source charge storage switch provided between a second capacitor element connection node to which one end of a second capacitor element can be connected and a source voltage output node to which a voltage of a source line of the electro-optical device is supplied, and a node short circuit switch provided between the common electrode voltage output node and the source voltage output node.

Display driver, electro-optical device, and electronic instrument

An integrated circuit device includes a display memory and a data read control circuit. The data read control circuit controls data reading so that data of pixels corresponding to a plurality of signal lines is read out by N-time reading in one horizontal scan period of a display panel (N is an integer larger than 1). The display memory includes a plurality of sense amplifier cells respectively connected with a plurality of bitlines. L sense amplifier cells (L is an integer larger than 1) respectively connected with the bitlines of L memory cells adjacent in a first direction (wordline direction) in which wordlines extend are disposed along a second direction (bitline direction) in which the bitlines extend.

An integrated circuit device including first to Nth circuit blocks CBto CBN disposed along a first direction D, when the first direction Dis a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction Dis a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CBto CBN include at least one memory block MB which stores image data, and at least one data driver block DB which drives data lines. The memory block MB and the data driver block DB are disposed adjacent to each other along the first direction D

An integrated circuit device includes first to Nth circuit blocks CBto CBN disposed along a direction Dwhen a direction from a first side which is a short side of the integrated circuit device toward a third side opposite to the first side is a direction Dand a direction from a second side which is a long side of the integrated circuit device toward a fourth side opposite to the second side is a direction DAt least one of the circuit blocks on both ends of the circuit blocks CBto CBN is a scan driver block for driving a scan line. Or, the scan driver block SB is disposed along the direction Don the side of the first to Nth circuit blocks in the direction D

In an integrated circuit device, a data line driver block which drives data lines of a display panel based on data supplied from a RAM block from which data is read N times (N is an integer larger than one) in one horizontal scan period 1H of the display panel includes first to N-th divided data line driver blocks disposed along a first direction in which bitlines extend. When data supplied from the RAM block is M bits (M is an integer larger than 1) and grayscale of a pixel corresponding to the data line is G bits, each of the first to N-th divided data line driver blocks includes (M/G) (multiple of three) data line driver cells which drive (M/G) data lines. (M/3G) R data line driver cells are provided in a first subdivided driver, (M/3G) G data line driver cells are provided in a second subdivided driver, and (M/3G) B data line driver cells are provided in a third subdivided driver.

A reference clock signal generation circuit for generating a reference clock signal for a charge-pump operation which raises or lowers a voltage includes a clock signal generation circuit which generates a reference clock signal having one of first to nth (n is an integer of two or more) frequencies, a wait time setting register in which a value corresponding to a wait time is set, and a frequency setting register in which a value corresponding to one of the first to nth frequencies is set. The clock signal generation circuit generates the reference clock signal having a predetermined frequency in a start period from start of the charge-pump operation to completion of the wait time, and generates the reference clock signal having a frequency corresponding to the value set in the frequency setting register in an operation period after the start period.

Reference clock signal generation circuit, power supply circuit, driver circuit, and electro-optical device

An integrated circuit device includes: first to Nth circuit blocks CBto CBN disposed along a direction D, the circuit blocks CBto CBN includes a data driver block DB. A data driver DR included in the data driver block DB includes Q driver cells DRCto DRCQ arranged along a direction Deach of the driver cells outputting a data signal corresponding to image data for one pixel. When a width of each of the driver cells DRCto DRCQ in the direction Dis WD, each of the circuit blocks CBto CBN has a width WB in the direction Dof 'Q&#xd7;WD&#x2266;WB&#x3c;(Q+1)&#xd7;WD'.

An integrated circuit device includes first to Nth circuit blocks CBto CBN disposed along a direction D, a first interface region provided on the Dside of the circuit blocks CBto CBN, and a second interface region provided on the Dside of the circuit blocks CBto CBN. The circuit blocks CBto CBN include a data driver block DB and a circuit block other than the data driver block DB. When the widths of the first interface region, the circuit blocks CBto CBN, and the second interface region in the direction Dare respectively W, WB, and W, the integrated circuit device has a width W in the direction Dof 'W+WB+W&#x2266;W&#x3c;W+2&#xd7;WB+W

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Chino, Japan

Kazuhiro Maekawa