Hitachi, Ltd.

Renesas Technology Corp.

Other

Hitachi Microcomputer Engineering, Ltd.

Hitachi Ulsi Systems Co., Ltd.

Hitachi Device Engineering Co., Ltd.

Kazuhiro Komori

Satoshi Meguro

Hitoshi Kume

Toshiaki Nishimoto

Kousuke Okuyama

Yoshiaki Kamigaki

Shoji Shukuri

Hideaki Yamamoto

June Sugiura

Katsuhiko Kubota

Kenichi Kuroda

Toshihisa Tsukada

Takaaki Hagiwara

Yasunobu Kosa

Shinji Shimizu

Hisao Katto

Ken Uchida

Akio Nishida

Tetsuo Adachi

Yasuko Yoshida

Tadashi Muto

Koichi Imato

Kouichi Kusuyama

Noriyuki Yabuoshi

Sousuke Tsuji

Hideo Miwa

Mitsuhiro Higuchi

Toshiko Koizumi

Hideaki Takahashi

Masataka Kato

Takeshi Wada

Minoru Fukuda

Tsutomu Okazaki

Satoru Ito

Toshimasa Kihara

Yuji Hara

Kiyofumi Uchibori

Harumi Wakimoto

Toshihisa Tsukuda

Hideo Tobe

Syoji Syukuri

A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The erasable non-volatile memory cell each includes a MIS transistor having a floating gate having a first level polycrystalline silicon layer, a source, and a drain coupled to the corresponding data line, and a control gate formed of a semiconductor region in the semiconductor substrate, the control gate being coupled to the corresponding word line.

Semiconductor integrated circuit and nonvolatile memory element

A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

Method of manufacturing a semiconductor integrated circuit device having single-element type non-volatile memory elements

Semiconductor integrated circuit device having single-element type non-volatile memory elements

Method of manufacturing a semiconductor memory device having a non-volatile memory cell portion with single misfet transistor type memory cells and a peripheral circuit portion with misfets

0 Owing to the above, even with the single-layer gate process such as single-layer polysilicon gate process, it is possible to obtain a semiconductor integrated circuit such as system LSI in which a nonvolatile memory which is excellent in data retention capability is merged and packaged with a DRAM etc. Further, since the nonvolatile memory of high reliability can be formed without adding any step to a related art manufacturing process, such as a standard CMOS manufacturing process, the present invention may be readily applied to an LSI in which the nonvolatile memory and a logic LSI, or the nonvolatile memory and a DRAM are merged and packaged on an identical semiconductor substrate. Accordingly, a system LSI in which a flash memory is merged and packaged can be provided without increasing the cost of manufacture.

A gate electrode of each MISFET is formed on a substrate in an active region whose periphery is defined by an element isolation trench, and crosses the active region so as to extend from one end thereof to the other end thereof. The gate electrode has a gate length in a boundary region defined between the active region and the element isolation trench which is greater than a gate length in a central portion of the active region. The gate electrode is configured in an H-type flat pattern. Further, the gate electrode covers the whole of one side extending along a gate-length direction, of the boundary region defined between the active region L and the element isolation trench, and parts of two sides thereof extending along a gate-width direction. The MISFETs are formed in electrically separated wells and are connected in series to constitute part of a reference voltage generating circuit.

Semiconductor integrated circuit device including MISFETs each with a gate electrode extended over a boundary region between an active region and an element isolation trench

Method of manufacturing a semiconductor memory device having a memory cell portion including MISFETs with a floating gate and a peripheral circuit portion with MISFETs

Owing to the above, even with the single-layer gate process such as single-layer polysilicon gate process, it is possible to obtain a semiconductor integrated circuit such as system LSI in which a nonvolatile memory which is excellent in data retention capability is merged and packaged with a DRAM etc. Further, since the nonvolatile memory of high reliability can be formed without adding any step to a related art manufacturing process, such as a standard CMOS manufacturing process, the present invention may be readily applied to an LSI in which the nonvolatile memory and a logic LSI, or the nonvolatile memory and a DRAM are merged and packaged on an identical semiconductor substrate. Accordingly, a system LSI in which a flash memory is merged and packaged can be provided without increasing the cost of manufacture.

An information retention capability based on a memory cell which includes pair of nonvolatile memory elements in a differential form is improved. A nonvolatile memory element ( ) constituting a flash memory is so constructed that its tunnel oxide film (GO ) and floating gate electrode (FGT) are respectively formed by utilizing the gate oxide film (GT ) and gate electrode (GT ) of a transistor for a circuit which is formed on the same semiconductor substrate as that of the element ( ). A memory cell is constructed in a 2-cells/1-bit scheme in which a pair of nonvolatile memory elements can be respectively connected to a pair of complementary data lines, and threshold voltage states different from each other are set for the nonvolatile memory elements so as to differentially read out data. A word line voltage in a readout mode is set to be substantially equal to a threshold voltage in a thermal equilibrium state (an initial threshold voltage), and also to be substantially equal to the average value of a low threshold voltage value and a high threshold voltage value. Thus, a data retention capability is enhanced to realize lowering in the rate of readout faults.

Semiconductor integrated circuit device

An information retention capability based on a memory cell which includes a pair of nonvolatile memory elements in a differential form is improved. A nonvolatile memory element ( ) constituting a flash memory is so constructed that its tunnel oxide film (G ) and floating gate electrode (FGT) are respectively formed by utilizing the gate oxide film (GT ) and gate electrode (GT ) of a transistor for a circuit which is formed on the same semiconductor substrate as that of the element ( ). A memory cell is constructed in a 2-cells/1-bit scheme in which a pair of nonvolatile memory elements can be respectively connected to a pair of complementary data lines, and threshold voltage states different from each other are set for the nonvolatile memory elements so as to differentially read out data. A word line voltage in a readout mode is set to be substantially equal to a threshold voltage in a thermal equilibrium state (an initial threshold voltage), and also to be substantially equal to the average value of a low threshold voltage value and a high threshold voltage value. Thus, a data retention capability is enhanced to realize lowering in the rate of readout faults.

An information retention capability based on a memory cell which includes a pair of nonvolatile memory elements in a differential form is improved. A nonvolatile memory element ( ) constituting a flash memory is so constructed that its tunnel oxide film (GO ) and floating gate electrode (FGT) are respectively formed by utilizing the gate oxide film (GT ) and gate electrode (GT ) of a transistor for a circuit which is formed on the same semiconductor substrate as that of the element ( ). A memory cell is constructed in a 2-cells/1-bit scheme in which a pair of nonvolatile memory elements can be respectively connected to a pair of complementary data lines, and threshold voltage states different from each other are set for the nonvolatile memory elements so as to differentially read out data. A word line voltage in a readout mode is set to be substantially equal to a threshold voltage in a thermal equilibrium state (an initial threshold voltage), and also to be substantially equal to the average value of a low threshold voltage value and a high threshold voltage value. Thus, a data retention capability is enhanced to realize lowering in the rate of readout faults.

Growing community of inventors

Musashimurayama, Japan

Kazuhiro Komori