Sanyo Electric Co., Ltd.

Sanyo Semiconductor Co., Ltd.

Kazuhiro Kimura

Takahiko Masumoto

Shigeaki Hayashibe

Toshiyuki Ozawa

Yutaka Hirakoso

Hiroshi Kaneko

Tatsuo Hiramatsu

Shizuka Ishimura

Munehiro Suka

Yoshikazu Tomida

Syugo Yamashita

Yoshihiko Kon

Akira Yamazaki

Ryoji Sakiyama

Takayuki Ohashi

Takahiro Takeda

Hiroyoshi Kaneyama

A filtering integrated circuit comprises: a storing circuit; a filter coefficient calculating unit configured to receive frequency information that identifies a characteristic frequency of an output signal in a filtering process, and to set filter coefficients calculated based on the frequency information in the storing circuit; and a filtering unit configured to output the output signal after applying a filtering process to an inputted signal based on the filter coefficients set in the storing circuit.

Filtering integrated circuit

A DA converter comprises a high-pass filter that outputs a multibit digital signal with a predetermined frequency or lower thereof attenuated if a signal level of the input multibit digital signal is less than a predetermined threshold, the high-pass filter outputting the multibit digital signal without attenuation if the signal level is at the threshold or higher; a &#x394;&#x3a3; modulator that performs &#x394;&#x3a3; modulation of the signal output from the filter unit; a dynamic element matching circuit that divides the signal output from the &#x394;&#x3a3; modulator to a plurality of signals; and a plurality of internal DA converters that convert the plurality of signals output from the dynamic element matching circuit to an analog signal.

Multibit &#x394;&#x3a3; modulation DA converter

Data counters and perform a counting operation which is synchronized with the respective timing of receiving multiplex data from a VICS data broadcasting station and a D-GPS data broadcasting station. While receiving the multiplex data from the VICS data broadcasting station, based on an output C of the data counter and a BIC detection output BP, block synchronization is detected. When the broadcasting station is switched from the VICS data broadcasting station to the D-GPS data broadcasting station, an output C of the data counter is selected in response to a control signal CONT and block synchronization is detected based on an output C and an output BP. Further, an output C is always inputted to the block counter. Thus, even while receiving the multiplex data from the D-GPS data broadcasting station, frame synchronization of the multiplex data of the VICS data broadcasting station is detected without causing miscounting.

Synchronous circuit of FM multiplex broadcasting receiver

A receiver receives FM multiplex broadcast data of both RDS and DARC systems by using one front end. A BIC detection circuit ( ) detects a block identification code (BIC) included in received data. A coincidence/non-coincidence detection circuit ( ) judges whether or not a BIC detection timing is correct and emits a coincidence/non-coincidence pulse. A forward protection circuit ( ) counts a frequency of outputs of non-coincidence pulses and retains an established synchronous condition until the counted value exceeds a predetermined value. Then, a forward protection control circuit ( ) inhibits the forward protection circuit from performing a count operation while a search is performed for selecting a station. Also, a rearward protection circuit ( ) counts a frequency of outputs of coincidence pulses and establishes a synchronous condition when the counted value reaches a predetermined value. Further, a rearward protection control circuit ( ) inhibits the rearward protection circuit from performing a count operation while a search is performed.

Synchronous circuit for FM multiple broadcast receiver

For frequency change, the VCO is controlled through a sub-charge pump circuit to make a determination as to whether or not a difference of dividing data between before and after the change is within a predetermined range. When it is determined that the difference is outside the predetermined range, the loop filer is forcibly charged in a charge time which is determined proportional to the difference in the dividing data, to thereby control an oscillation frequency of the VOC. A large VOC oscillation frequency change can be swiftly realized. Also, while the frequency change circuit is controlling the oscillation frequency, a time constant of the loop filter in the PLL circuit is preferably set at a small value, so that frequency change by the frequency change circuit can be swiftly achieved.

PLL synthesizer circuit

Received signals are digitized by a comparator, and sampled by regenerated clock signals synchronized to a carrier. Biphase symbol data are demodulated based on the sampling data. A biphase decoder circuit performs subtraction of the biphase symbol data to be paired. The subtraction result is compared with threshold values by data judgment circuitry which then judges inversion of the biphase signals to be paired. An RDS-ID detector circuit detects inversion of RDS signals by detection of either continuity or a ratio of signals received for a certain length period. Alternatively, RDS signals are detected by stability of output from the pair judgment circuit to detect a combination of biphase symbols.

RDS signal detection device

A second random number generator (102) sets a scramble key data included in a transmitted/received data to an initial value, and it generates predetermined second random numbers. A first random number generator (101) generates first random numbers from the second random numbers supplied by the second random number generator (102). The generation of the first random numbers by the first random number generator (101) is controlled by an output from a first control circuit (103). Since the output from the first control circuit (103) is changed in accordance with a service identification code SI, the first random numbers generated from the first random number generator (101) are changed. The first random numbers are input to a gate circuit (105) via a second control circuit (104). The second control circuit (104) inhibits the output of the first random numbers in accordance with the SI value. In such a manner, scrambling or descrambling is controlled in the gate circuit (105).

Data processor for FM multiplex broadcast

An RDS signal is binarized by a comparator (2) and the output is sampled by a regeneration clock in synchronism with a regeneration carrier to provide sampled data. Then, by means of an accumulator (an adder 6 and a D-FF7) or a low pass filter (12), an integration result of the sampled output is obtained for each biphase symbol and by means of a biphase decoder circuit (9), the integration results are subjected to a subtraction between two symbols making up a pair. A differentially coded RDS data can be obtained using the sign of the subtraction result, which is differentially decoded in a differential decoder circuit (11) to provide an RDS data. In addition, the absolute value of the subtraction result is compared with a predetermined threshold value to provide reliability data for each differentially coded RDS data using the comparison result. The lower one of the consecutive reliability data may be assumed to be the reliability data for the RDS data.

Data demodulator device

A demodulating circuit demodulates a received signal, and outputs patterns of demodulated data and reliability information bits indicating correctness of the demodulated data. These are supplied to first and second shift registers (4 and 5), respectively. When the number of reliability information bits of Level 1 in the second shift register is a predetermined value or less, a shift operation is repeated a plurality of times. When a reliability information bit of Level 1 is outputted, an error correction control circuit (7) successively outputs all possible bit patterns of the demodulated data An EXOR gate (10) generates all possible patterns of demodulated data An error correcting circuit (11) carries out error correction for all the patterns. When the number is larger than the predetermined value, the error correction is carried out only for the demodulated data supplied from the demodulating circuit in a conventional manner.

Error correction device

Superimposed FM data is demodulated to digital data. A synchronism reproducing circuit (data block detecting section) detects the front of blocks in the digital data to generate a block head signal (a station change timing signal), which is supplied to a control section of a station selecting microcomputer. When a station selecting key requests a change of the received station, station data corresponding to a requested station is supplied to the control section (a station selecting control section). When the block head signal is inputted after requesting the change of the station, the control section begins to output station change data to a PLL frequency synthesizer in order to change the frequency signal in a front end. This prevents a latter part of a block in received superimposed FM data from being NG data.

FM radio receiver and signal processing device used therein

A scrambling key is generated from demodulated and error-corrected FM demodulation data for use in descrambling. During this process, if error correction has not been normally conducted to an object data packet, a subsequent descrambling operation is not executed to that data packet. In addition, a descrambling operation is not carried out if the object data packet is a parity packet.

Data processing device for FM multi-channel broadcasting

In a packet analyzing circuit, first and second key data are detected and stored in respective first and second key data registers. First and second key generation circuits generate first and second keys from the first and second key data. An exclusive OR operation is carried out to both keys so as to generate a scrambling key. Using the scrambling key as an initial value, a random number generator generates a PN code used for scrambling, so that scrambled data is descrambled by adding the PN code to the data. The first key generation circuit, which receives a control signal CON from a timing generation circuit, is controlled by the control signal CON such that a scrambling key is generated only when the random number generator needs an initial value.

Descrambling device

An offset circuit (2) detects an offset word serving as a synchronization pattern. By being triggered by the detection, main and subordinate synchronization detection circuits (5 and 6) detect the periodicity of the offset word only during a predetermined backward guard period. Both synchronization detection circuits (5 and 6) detect offset words at different timings. Therefore, if one synchronization detection circuit (5 or 6) fails in detection of synchronization, it is possible to use a detection result of the other synchronization detection circuit (5 or 6). Moreover, received data during the backward guard period is stored in a data memory (11). Therefore, it is possible to use the stored data as received data after detection of synchronization. Even after establishment of synchronization, the synchronization detection circuit (5 or 6) continuously detects the periodicity of an offset word at a timing different from an established timing. Therefore, when established synchronization is incorrect, it can immediately be corrected.

Synchronization regeneration circuit

In accordance with the operation of an operating section 14, a control section 12 performs a reception control operation and demodulates a signal passing through a band pass filter 7 for extracting a multiplex signal using a multiplex signal demodulating section 8 when receiving a broadcast signal. A block synchronization circuit 16 of a synchronization circuit 9 carries out block synchronization processing on the demodulated signal. When block synchronization is established, a synchronization determination signal is supplied to a detecting section DET and the detecting section DET determines that a broadcasting station whose radio waves are currently being received is a multiplex broadcasting station.

FM multiplex broadcast receiving circuit for detecting presence or

In a decoding processing circuit of a digital signal receiver, a first comparison circuit detects that a prefix of packet data is inputted in a shift register on the basis of a count value of a counter circuit. In response to the result of detection, a pseudo-random binary sequence generation circuit outputs a pseudo-random binary sequence on the basis of a data group number and a data packet number outputted from the shift register and key data previously extracted by a key data fetch circuit. When a second comparison circuit detects that block data in the data packet is inputted in the shift register, an exclusive OR circuit exclusively ORs the pseudo-random binary sequence with receive data, so that decoded data is inputted in the shift register.

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Fukaya, Japan

Kazuhiro Kimura